---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- CPU model
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-- CPU model
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--
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--
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-- Part of the LXP32 instruction cache testbench
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-- Part of the LXP32 instruction cache testbench
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- Requests data from cache
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-- Requests data from cache
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use ieee.math_real.all;
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use work.common_pkg.all;
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use work.common_pkg.all;
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use work.tb_pkg.all;
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use work.tb_pkg.all;
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entity cpu_model is
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entity cpu_model is
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generic(
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generic(
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BLOCKS: integer;
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BLOCKS: integer;
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VERBOSE: boolean
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VERBOSE: boolean
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);
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);
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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lli_re_o: out std_logic;
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lli_re_o: out std_logic;
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lli_adr_o: out std_logic_vector(29 downto 0);
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lli_adr_o: out std_logic_vector(29 downto 0);
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lli_dat_i: in std_logic_vector(31 downto 0);
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lli_dat_i: in std_logic_vector(31 downto 0);
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lli_busy_i: in std_logic;
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lli_busy_i: in std_logic;
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finish_o: out std_logic
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finish_o: out std_logic
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);
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);
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end entity;
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end entity;
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architecture sim of cpu_model is
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architecture sim of cpu_model is
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constant bursts: integer:=10000;
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constant bursts: integer:=10000;
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signal re: std_logic:='0';
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signal re: std_logic:='0';
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signal lli_adr: std_logic_vector(29 downto 0);
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signal lli_adr: std_logic_vector(29 downto 0);
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signal request: std_logic:='0';
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signal request: std_logic:='0';
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signal request_addr: std_logic_vector(29 downto 0);
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signal request_addr: std_logic_vector(29 downto 0);
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signal finish: std_logic:='0';
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signal finish: std_logic:='0';
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signal current_latency: integer:=1;
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signal current_latency: integer:=1;
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signal max_latency: integer:=-1;
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signal max_latency: integer:=-1;
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signal total_latency: integer:=0;
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signal total_latency: integer:=0;
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signal spurious_misses: integer:=0;
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signal spurious_misses: integer:=0;
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begin
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begin
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process is
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process is
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variable b: integer:=1;
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variable b: integer:=1;
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variable start: integer;
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variable start: integer;
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variable size: integer;
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variable size: integer;
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variable addr: integer:=0;
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variable addr: integer:=0;
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variable delay: integer;
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variable delay: integer;
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variable rng_state: rng_state_type;
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variable rng_state: rng_state_type;
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variable r: integer;
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variable r: integer;
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variable total_requests: integer:=0;
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variable total_requests: integer:=0;
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begin
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begin
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while b<=BLOCKS loop
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while b<=BLOCKS loop
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rand(rng_state,1,10,r);
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rand(rng_state,1,10,r);
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if r=1 then -- insert large block occasionally
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if r=1 then -- insert large block occasionally
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rand(rng_state,1,400,size);
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rand(rng_state,1,400,size);
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else -- small block
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else -- small block
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rand(rng_state,1,32,size);
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rand(rng_state,1,32,size);
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end if;
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end if;
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rand(rng_state,0,1,r);
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rand(rng_state,0,1,r);
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if r=0 then -- long jump
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if r=0 then -- long jump
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rand(rng_state,0,1024,start);
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rand(rng_state,0,1024,start);
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addr:=start;
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addr:=start;
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if VERBOSE then
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if VERBOSE then
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report "Fetching block #"&integer'image(b)&" at address "&integer'image(addr)&
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report "Fetching block #"&integer'image(b)&" at address "&integer'image(addr)&
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" of size "&integer'image(size);
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" of size "&integer'image(size);
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end if;
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end if;
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else -- short jump
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else -- short jump
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rand(rng_state,-10,10,r);
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rand(rng_state,-10,10,r);
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start:=addr+r;
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start:=addr+r;
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if start<0 then
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if start<0 then
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start:=0;
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start:=0;
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end if;
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end if;
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addr:=start;
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addr:=start;
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if VERBOSE then
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if VERBOSE then
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report "Fetching block #"&integer'image(b)&" at address "&integer'image(addr)&
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report "Fetching block #"&integer'image(b)&" at address "&integer'image(addr)&
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" of size "&integer'image(size)&" (short jump)";
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" of size "&integer'image(size)&" (short jump)";
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end if;
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end if;
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end if;
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end if;
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while addr<start+size loop
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while addr<start+size loop
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re<='1';
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re<='1';
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total_requests:=total_requests+1;
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total_requests:=total_requests+1;
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lli_adr<=std_logic_vector(to_unsigned(addr,30));
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lli_adr<=std_logic_vector(to_unsigned(addr,30));
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wait until rising_edge(clk_i) and lli_busy_i='0';
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wait until rising_edge(clk_i) and lli_busy_i='0';
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re<='0';
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re<='0';
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addr:=addr+1;
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addr:=addr+1;
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rand(rng_state,0,4,delay);
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rand(rng_state,0,4,delay);
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if delay>0 then
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if delay>0 then
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for i in 1 to delay loop
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for i in 1 to delay loop
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wait until rising_edge(clk_i);
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wait until rising_edge(clk_i);
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end loop;
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end loop;
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end if;
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end if;
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end loop;
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end loop;
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if (b mod 10000)=0 then
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if (b mod 10000)=0 then
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report integer'image(b)&" BLOCKS PROCESSED";
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report integer'image(b)&" BLOCKS PROCESSED";
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end if;
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end if;
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b:=b+1;
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b:=b+1;
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end loop;
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end loop;
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report "Number of requests: "&integer'image(total_requests);
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report "Number of requests: "&integer'image(total_requests);
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report "Maximum latency: "&integer'image(max_latency);
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report "Maximum latency: "&integer'image(max_latency);
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report "Average latency: "&real'image(real(total_latency)/real(total_requests));
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report "Average latency: "&real'image(real(total_latency)/real(total_requests));
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report "Number of spurious misses: "&integer'image(spurious_misses);
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report "Number of spurious misses: "&integer'image(spurious_misses);
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finish<='1';
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finish<='1';
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wait;
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wait;
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end process;
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end process;
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lli_re_o<=re;
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lli_re_o<=re;
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lli_adr_o<=lli_adr;
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lli_adr_o<=lli_adr;
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if lli_busy_i='0' then
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if lli_busy_i='0' then
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if request='1' then
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if request='1' then
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assert lli_dat_i=(("00"&request_addr) xor xor_constant)
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assert lli_dat_i=(("00"&request_addr) xor xor_constant)
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report "Data mismatch: expected 0x"&
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report "Data mismatch: expected 0x"&
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hex_string(("00"&request_addr) xor xor_constant)&
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hex_string(("00"&request_addr) xor xor_constant)&
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", got 0x"&hex_string(lli_dat_i)
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", got 0x"&hex_string(lli_dat_i)
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severity failure;
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severity failure;
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end if;
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end if;
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request<=re;
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request<=re;
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request_addr<=lli_adr;
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request_addr<=lli_adr;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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finish_o<=finish;
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finish_o<=finish;
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-- Measure latency
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-- Measure latency
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if lli_busy_i='0' then
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if lli_busy_i='0' then
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if request='1' then
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if request='1' then
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total_latency<=total_latency+current_latency;
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total_latency<=total_latency+current_latency;
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if current_latency>max_latency then
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if current_latency>max_latency then
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max_latency<=current_latency;
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max_latency<=current_latency;
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end if;
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end if;
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end if;
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end if;
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current_latency<=1;
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current_latency<=1;
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else
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else
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if lli_dat_i=(("00"&request_addr) xor xor_constant) and current_latency=1 then
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if lli_dat_i=(("00"&request_addr) xor xor_constant) and current_latency=1 then
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spurious_misses<=spurious_misses+1;
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spurious_misses<=spurious_misses+1;
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end if;
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end if;
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current_latency<=current_latency+1;
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current_latency<=current_latency+1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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assert lli_busy_i='0' or request='1'
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assert lli_busy_i='0' or request='1'
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report "LLI busy signal asserted without a request"
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report "LLI busy signal asserted without a request"
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severity failure;
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severity failure;
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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