/*
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/*
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* Test for temporarily blocked interrupts
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* Test for temporarily blocked interrupts
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*/
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*/
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lc r100, 0x10000000 // test result output pointer
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lc r100, 0x10000000 // test result output pointer
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lc r101, halt
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lc r101, halt
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lc r102, failure
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lc r102, failure
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lc r103, 0x20000000 // timer: number of pulses (0xFFFFFFFF - infinite)
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lc r103, 0x20000000 // timer: number of pulses (0xFFFFFFFF - infinite)
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lc r104, 0x20000004 // timer: delay between pulses (in cycles)
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lc r104, 0x20000004 // timer: delay between pulses (in cycles)
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lc iv0, timer_handler
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lc iv0, timer_handler
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lc cr, 0x101 // enable interrupt 0 in temporarily blocked state
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lc cr, 0x101 // enable interrupt 0 in temporarily blocked state
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lc r32, 0 // interrupt handler call counter
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lc r32, 0 // interrupt handler call counter
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lc r33, 1000 // loop counter
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lc r33, 1000 // loop counter
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lc r34, loop1
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lc r34, loop1
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lc r35, loop2
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lc r35, loop2
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sw r104, 100
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sw r104, 100
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sw r103, 1
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sw r103, 1
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loop1:
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loop1:
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sub r33, r33, 1
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sub r33, r33, 1
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cjmpug r34, r33, 0 // loop1
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cjmpug r34, r33, 0 // loop1
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lc r33, 1000
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lc r33, 1000
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mov cr, 1 // unblock interrupt 0
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mov cr, 1 // unblock interrupt 0
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loop2:
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loop2:
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sub r33, r33, 1
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sub r33, r33, 1
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cjmpug r35, r33, 0 // loop2
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cjmpug r35, r33, 0 // loop2
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// r32 should be 1 by this point
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// r32 should be 1 by this point
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cjmpne r102, r32, 1 // failure
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cjmpne r102, r32, 1 // failure
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sw r100, 1
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sw r100, 1
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jmp r101 // halt
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jmp r101 // halt
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failure:
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failure:
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sw r100, 2
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sw r100, 2
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halt:
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halt:
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hlt
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hlt
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jmp r101 // halt
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jmp r101 // halt
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timer_handler:
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timer_handler:
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add r32, r32, 1
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add r32, r32, 1
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iret
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iret
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