---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
-- Simple WISHBONE interconnect
|
-- Simple WISHBONE interconnect
|
--
|
--
|
-- Generated by wigen at 02/16/16 06:15:08
|
-- Generated by wigen at 02/16/16 06:15:08
|
--
|
--
|
-- Configuration:
|
-- Configuration:
|
-- Number of masters: 2
|
-- Number of masters: 2
|
-- Number of slaves: 4
|
-- Number of slaves: 4
|
-- Master address width: 32
|
-- Master address width: 32
|
-- Slave address width: 28
|
-- Slave address width: 28
|
-- Port size: 32
|
-- Port size: 32
|
-- Port granularity: 8
|
-- Port granularity: 8
|
-- Entity name: intercon
|
-- Entity name: intercon
|
-- Pipelined arbiter: no
|
-- Pipelined arbiter: no
|
-- Registered feedback: no
|
-- Registered feedback: no
|
-- Unsafe slave decoder: no
|
-- Unsafe slave decoder: no
|
--
|
--
|
-- Command line:
|
-- Command line:
|
-- wigen -e intercon 2 4 32 28 32 8
|
-- wigen -e intercon 2 4 32 28 32 8
|
---------------------------------------------------------------------
|
---------------------------------------------------------------------
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
|
entity intercon is
|
entity intercon is
|
port(
|
port(
|
clk_i: in std_logic;
|
clk_i: in std_logic;
|
rst_i: in std_logic;
|
rst_i: in std_logic;
|
|
|
s0_cyc_i: in std_logic;
|
s0_cyc_i: in std_logic;
|
s0_stb_i: in std_logic;
|
s0_stb_i: in std_logic;
|
s0_we_i: in std_logic;
|
s0_we_i: in std_logic;
|
s0_sel_i: in std_logic_vector(3 downto 0);
|
s0_sel_i: in std_logic_vector(3 downto 0);
|
s0_ack_o: out std_logic;
|
s0_ack_o: out std_logic;
|
s0_adr_i: in std_logic_vector(31 downto 2);
|
s0_adr_i: in std_logic_vector(31 downto 2);
|
s0_dat_i: in std_logic_vector(31 downto 0);
|
s0_dat_i: in std_logic_vector(31 downto 0);
|
s0_dat_o: out std_logic_vector(31 downto 0);
|
s0_dat_o: out std_logic_vector(31 downto 0);
|
|
|
s1_cyc_i: in std_logic;
|
s1_cyc_i: in std_logic;
|
s1_stb_i: in std_logic;
|
s1_stb_i: in std_logic;
|
s1_we_i: in std_logic;
|
s1_we_i: in std_logic;
|
s1_sel_i: in std_logic_vector(3 downto 0);
|
s1_sel_i: in std_logic_vector(3 downto 0);
|
s1_ack_o: out std_logic;
|
s1_ack_o: out std_logic;
|
s1_adr_i: in std_logic_vector(31 downto 2);
|
s1_adr_i: in std_logic_vector(31 downto 2);
|
s1_dat_i: in std_logic_vector(31 downto 0);
|
s1_dat_i: in std_logic_vector(31 downto 0);
|
s1_dat_o: out std_logic_vector(31 downto 0);
|
s1_dat_o: out std_logic_vector(31 downto 0);
|
|
|
m0_cyc_o: out std_logic;
|
m0_cyc_o: out std_logic;
|
m0_stb_o: out std_logic;
|
m0_stb_o: out std_logic;
|
m0_we_o: out std_logic;
|
m0_we_o: out std_logic;
|
m0_sel_o: out std_logic_vector(3 downto 0);
|
m0_sel_o: out std_logic_vector(3 downto 0);
|
m0_ack_i: in std_logic;
|
m0_ack_i: in std_logic;
|
m0_adr_o: out std_logic_vector(27 downto 2);
|
m0_adr_o: out std_logic_vector(27 downto 2);
|
m0_dat_o: out std_logic_vector(31 downto 0);
|
m0_dat_o: out std_logic_vector(31 downto 0);
|
m0_dat_i: in std_logic_vector(31 downto 0);
|
m0_dat_i: in std_logic_vector(31 downto 0);
|
|
|
m1_cyc_o: out std_logic;
|
m1_cyc_o: out std_logic;
|
m1_stb_o: out std_logic;
|
m1_stb_o: out std_logic;
|
m1_we_o: out std_logic;
|
m1_we_o: out std_logic;
|
m1_sel_o: out std_logic_vector(3 downto 0);
|
m1_sel_o: out std_logic_vector(3 downto 0);
|
m1_ack_i: in std_logic;
|
m1_ack_i: in std_logic;
|
m1_adr_o: out std_logic_vector(27 downto 2);
|
m1_adr_o: out std_logic_vector(27 downto 2);
|
m1_dat_o: out std_logic_vector(31 downto 0);
|
m1_dat_o: out std_logic_vector(31 downto 0);
|
m1_dat_i: in std_logic_vector(31 downto 0);
|
m1_dat_i: in std_logic_vector(31 downto 0);
|
|
|
m2_cyc_o: out std_logic;
|
m2_cyc_o: out std_logic;
|
m2_stb_o: out std_logic;
|
m2_stb_o: out std_logic;
|
m2_we_o: out std_logic;
|
m2_we_o: out std_logic;
|
m2_sel_o: out std_logic_vector(3 downto 0);
|
m2_sel_o: out std_logic_vector(3 downto 0);
|
m2_ack_i: in std_logic;
|
m2_ack_i: in std_logic;
|
m2_adr_o: out std_logic_vector(27 downto 2);
|
m2_adr_o: out std_logic_vector(27 downto 2);
|
m2_dat_o: out std_logic_vector(31 downto 0);
|
m2_dat_o: out std_logic_vector(31 downto 0);
|
m2_dat_i: in std_logic_vector(31 downto 0);
|
m2_dat_i: in std_logic_vector(31 downto 0);
|
|
|
m3_cyc_o: out std_logic;
|
m3_cyc_o: out std_logic;
|
m3_stb_o: out std_logic;
|
m3_stb_o: out std_logic;
|
m3_we_o: out std_logic;
|
m3_we_o: out std_logic;
|
m3_sel_o: out std_logic_vector(3 downto 0);
|
m3_sel_o: out std_logic_vector(3 downto 0);
|
m3_ack_i: in std_logic;
|
m3_ack_i: in std_logic;
|
m3_adr_o: out std_logic_vector(27 downto 2);
|
m3_adr_o: out std_logic_vector(27 downto 2);
|
m3_dat_o: out std_logic_vector(31 downto 0);
|
m3_dat_o: out std_logic_vector(31 downto 0);
|
m3_dat_i: in std_logic_vector(31 downto 0)
|
m3_dat_i: in std_logic_vector(31 downto 0)
|
);
|
);
|
end entity;
|
end entity;
|
|
|
architecture rtl of intercon is
|
architecture rtl of intercon is
|
|
|
signal request: std_logic_vector(1 downto 0);
|
signal request: std_logic_vector(1 downto 0);
|
signal grant_next: std_logic_vector(1 downto 0);
|
signal grant_next: std_logic_vector(1 downto 0);
|
signal grant: std_logic_vector(1 downto 0);
|
signal grant: std_logic_vector(1 downto 0);
|
signal grant_reg: std_logic_vector(1 downto 0):=(others=>'0');
|
signal grant_reg: std_logic_vector(1 downto 0):=(others=>'0');
|
|
|
signal select_slave: std_logic_vector(4 downto 0);
|
signal select_slave: std_logic_vector(4 downto 0);
|
|
|
signal cyc_mux: std_logic;
|
signal cyc_mux: std_logic;
|
signal stb_mux: std_logic;
|
signal stb_mux: std_logic;
|
signal we_mux: std_logic;
|
signal we_mux: std_logic;
|
signal sel_mux: std_logic_vector(3 downto 0);
|
signal sel_mux: std_logic_vector(3 downto 0);
|
signal adr_mux: std_logic_vector(31 downto 2);
|
signal adr_mux: std_logic_vector(31 downto 2);
|
signal wdata_mux: std_logic_vector(31 downto 0);
|
signal wdata_mux: std_logic_vector(31 downto 0);
|
|
|
signal ack_mux: std_logic;
|
signal ack_mux: std_logic;
|
signal rdata_mux: std_logic_vector(31 downto 0);
|
signal rdata_mux: std_logic_vector(31 downto 0);
|
|
|
begin
|
begin
|
|
|
-- ARBITER
|
-- ARBITER
|
-- Selects the active master. Masters with lower port numbers
|
-- Selects the active master. Masters with lower port numbers
|
-- have higher priority. Ongoing cycles are not interrupted.
|
-- have higher priority. Ongoing cycles are not interrupted.
|
|
|
request<=s1_cyc_i&s0_cyc_i;
|
request<=s1_cyc_i&s0_cyc_i;
|
|
|
grant_next<="01" when request(0)='1' else
|
grant_next<="01" when request(0)='1' else
|
"10" when request(1)='1' else
|
"10" when request(1)='1' else
|
(others=>'0');
|
(others=>'0');
|
|
|
grant<=grant_reg when (request and grant_reg)/="00" else grant_next;
|
grant<=grant_reg when (request and grant_reg)/="00" else grant_next;
|
|
|
process (clk_i) is
|
process (clk_i) is
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if rst_i='1' then
|
if rst_i='1' then
|
grant_reg<=(others=>'0');
|
grant_reg<=(others=>'0');
|
else
|
else
|
grant_reg<=grant;
|
grant_reg<=grant;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- MASTER->SLAVE MUX
|
-- MASTER->SLAVE MUX
|
|
|
cyc_mux<=(s0_cyc_i and grant(0)) or
|
cyc_mux<=(s0_cyc_i and grant(0)) or
|
(s1_cyc_i and grant(1));
|
(s1_cyc_i and grant(1));
|
|
|
stb_mux<=(s0_stb_i and grant(0)) or
|
stb_mux<=(s0_stb_i and grant(0)) or
|
(s1_stb_i and grant(1));
|
(s1_stb_i and grant(1));
|
|
|
we_mux<=(s0_we_i and grant(0)) or
|
we_mux<=(s0_we_i and grant(0)) or
|
(s1_we_i and grant(1));
|
(s1_we_i and grant(1));
|
|
|
sel_mux_gen: for i in sel_mux'range generate
|
sel_mux_gen: for i in sel_mux'range generate
|
sel_mux(i)<=(s0_sel_i(i) and grant(0)) or
|
sel_mux(i)<=(s0_sel_i(i) and grant(0)) or
|
(s1_sel_i(i) and grant(1));
|
(s1_sel_i(i) and grant(1));
|
end generate;
|
end generate;
|
|
|
adr_mux_gen: for i in adr_mux'range generate
|
adr_mux_gen: for i in adr_mux'range generate
|
adr_mux(i)<=(s0_adr_i(i) and grant(0)) or
|
adr_mux(i)<=(s0_adr_i(i) and grant(0)) or
|
(s1_adr_i(i) and grant(1));
|
(s1_adr_i(i) and grant(1));
|
end generate;
|
end generate;
|
|
|
wdata_mux_gen: for i in wdata_mux'range generate
|
wdata_mux_gen: for i in wdata_mux'range generate
|
wdata_mux(i)<=(s0_dat_i(i) and grant(0)) or
|
wdata_mux(i)<=(s0_dat_i(i) and grant(0)) or
|
(s1_dat_i(i) and grant(1));
|
(s1_dat_i(i) and grant(1));
|
end generate;
|
end generate;
|
|
|
-- MASTER->SLAVE DEMUX
|
-- MASTER->SLAVE DEMUX
|
|
|
select_slave<="00001" when adr_mux(31 downto 28)="0000" else
|
select_slave<="00001" when adr_mux(31 downto 28)="0000" else
|
"00010" when adr_mux(31 downto 28)="0001" else
|
"00010" when adr_mux(31 downto 28)="0001" else
|
"00100" when adr_mux(31 downto 28)="0010" else
|
"00100" when adr_mux(31 downto 28)="0010" else
|
"01000" when adr_mux(31 downto 28)="0011" else
|
"01000" when adr_mux(31 downto 28)="0011" else
|
"10000"; -- fallback slave
|
"10000"; -- fallback slave
|
|
|
m0_cyc_o<=cyc_mux and select_slave(0);
|
m0_cyc_o<=cyc_mux and select_slave(0);
|
m0_stb_o<=stb_mux and select_slave(0);
|
m0_stb_o<=stb_mux and select_slave(0);
|
m0_we_o<=we_mux;
|
m0_we_o<=we_mux;
|
m0_sel_o<=sel_mux;
|
m0_sel_o<=sel_mux;
|
m0_adr_o<=adr_mux(m0_adr_o'range);
|
m0_adr_o<=adr_mux(m0_adr_o'range);
|
m0_dat_o<=wdata_mux;
|
m0_dat_o<=wdata_mux;
|
|
|
m1_cyc_o<=cyc_mux and select_slave(1);
|
m1_cyc_o<=cyc_mux and select_slave(1);
|
m1_stb_o<=stb_mux and select_slave(1);
|
m1_stb_o<=stb_mux and select_slave(1);
|
m1_we_o<=we_mux;
|
m1_we_o<=we_mux;
|
m1_sel_o<=sel_mux;
|
m1_sel_o<=sel_mux;
|
m1_adr_o<=adr_mux(m1_adr_o'range);
|
m1_adr_o<=adr_mux(m1_adr_o'range);
|
m1_dat_o<=wdata_mux;
|
m1_dat_o<=wdata_mux;
|
|
|
m2_cyc_o<=cyc_mux and select_slave(2);
|
m2_cyc_o<=cyc_mux and select_slave(2);
|
m2_stb_o<=stb_mux and select_slave(2);
|
m2_stb_o<=stb_mux and select_slave(2);
|
m2_we_o<=we_mux;
|
m2_we_o<=we_mux;
|
m2_sel_o<=sel_mux;
|
m2_sel_o<=sel_mux;
|
m2_adr_o<=adr_mux(m2_adr_o'range);
|
m2_adr_o<=adr_mux(m2_adr_o'range);
|
m2_dat_o<=wdata_mux;
|
m2_dat_o<=wdata_mux;
|
|
|
m3_cyc_o<=cyc_mux and select_slave(3);
|
m3_cyc_o<=cyc_mux and select_slave(3);
|
m3_stb_o<=stb_mux and select_slave(3);
|
m3_stb_o<=stb_mux and select_slave(3);
|
m3_we_o<=we_mux;
|
m3_we_o<=we_mux;
|
m3_sel_o<=sel_mux;
|
m3_sel_o<=sel_mux;
|
m3_adr_o<=adr_mux(m3_adr_o'range);
|
m3_adr_o<=adr_mux(m3_adr_o'range);
|
m3_dat_o<=wdata_mux;
|
m3_dat_o<=wdata_mux;
|
|
|
-- SLAVE->MASTER MUX
|
-- SLAVE->MASTER MUX
|
|
|
ack_mux<=(m0_ack_i and select_slave(0)) or
|
ack_mux<=(m0_ack_i and select_slave(0)) or
|
(m1_ack_i and select_slave(1)) or
|
(m1_ack_i and select_slave(1)) or
|
(m2_ack_i and select_slave(2)) or
|
(m2_ack_i and select_slave(2)) or
|
(m3_ack_i and select_slave(3)) or
|
(m3_ack_i and select_slave(3)) or
|
(cyc_mux and stb_mux and select_slave(4)); -- fallback slave
|
(cyc_mux and stb_mux and select_slave(4)); -- fallback slave
|
|
|
rdata_mux_gen: for i in rdata_mux'range generate
|
rdata_mux_gen: for i in rdata_mux'range generate
|
rdata_mux(i)<=(m0_dat_i(i) and select_slave(0)) or
|
rdata_mux(i)<=(m0_dat_i(i) and select_slave(0)) or
|
(m1_dat_i(i) and select_slave(1)) or
|
(m1_dat_i(i) and select_slave(1)) or
|
(m2_dat_i(i) and select_slave(2)) or
|
(m2_dat_i(i) and select_slave(2)) or
|
(m3_dat_i(i) and select_slave(3));
|
(m3_dat_i(i) and select_slave(3));
|
end generate;
|
end generate;
|
|
|
-- SLAVE->MASTER DEMUX
|
-- SLAVE->MASTER DEMUX
|
|
|
s0_ack_o<=ack_mux and grant(0);
|
s0_ack_o<=ack_mux and grant(0);
|
s0_dat_o<=rdata_mux;
|
s0_dat_o<=rdata_mux;
|
|
|
s1_ack_o<=ack_mux and grant(1);
|
s1_ack_o<=ack_mux and grant(1);
|
s1_dat_o<=rdata_mux;
|
s1_dat_o<=rdata_mux;
|
|
|
end architecture;
|
end architecture;
|
|
|