---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Scrambler
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-- Scrambler
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--
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--
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-- Part of the LXP32 test platform
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-- Part of the LXP32 test platform
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- Generates a pseudo-random binary sequence using a Linear-Feedback
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-- Generates a pseudo-random binary sequence using a Linear-Feedback
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-- Shift Register (LFSR).
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-- Shift Register (LFSR).
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--
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--
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-- In order to generate a maximum-length sequence, 1+x^TAP1+x^TAP2
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-- In order to generate a maximum-length sequence, 1+x^TAP1+x^TAP2
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-- must be a primitive polynomial. Typical polynomials include:
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-- must be a primitive polynomial. Typical polynomials include:
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-- (6,7), (9,11), (14,15).
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-- (6,7), (9,11), (14,15).
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--
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--
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-- Note: regardless of whether this description is synthesizable,
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-- Note: regardless of whether this description is synthesizable,
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-- it was designed exclusively for simulation purposes.
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-- it was designed exclusively for simulation purposes.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity scrambler is
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entity scrambler is
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generic(
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generic(
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TAP1: integer;
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TAP1: integer;
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TAP2: integer
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TAP2: integer
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);
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);
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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ce_i: in std_logic;
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ce_i: in std_logic;
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d_o: out std_logic
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d_o: out std_logic
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);
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);
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end entity;
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end entity;
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architecture rtl of scrambler is
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architecture rtl of scrambler is
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signal reg: std_logic_vector(TAP2 downto 1):=(others=>'1');
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signal reg: std_logic_vector(TAP2 downto 1):=(others=>'1');
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begin
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begin
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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reg<=(others=>'1');
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reg<=(others=>'1');
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elsif ce_i='1' then
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elsif ce_i='1' then
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reg<=reg(TAP2-1 downto 1)&(reg(TAP2) xor reg(TAP1));
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reg<=reg(TAP2-1 downto 1)&(reg(TAP2) xor reg(TAP1));
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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d_o<=reg(1);
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d_o<=reg(1);
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end architecture;
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end architecture;
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