---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- Timer
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-- Timer
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--
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--
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-- Part of the LXP32 test platform
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-- Part of the LXP32 test platform
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- A simple programmable interval timer.
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-- A simple programmable interval timer.
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--
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--
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-- Note: regardless of whether this description is synthesizable,
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-- Note: regardless of whether this description is synthesizable,
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-- it was designed exclusively for simulation purposes.
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-- it was designed exclusively for simulation purposes.
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity timer is
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entity timer is
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port(
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port(
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clk_i: in std_logic;
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clk_i: in std_logic;
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rst_i: in std_logic;
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rst_i: in std_logic;
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wbs_cyc_i: in std_logic;
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wbs_cyc_i: in std_logic;
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wbs_stb_i: in std_logic;
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wbs_stb_i: in std_logic;
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wbs_we_i: in std_logic;
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wbs_we_i: in std_logic;
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wbs_sel_i: in std_logic_vector(3 downto 0);
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wbs_sel_i: in std_logic_vector(3 downto 0);
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wbs_ack_o: out std_logic;
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wbs_ack_o: out std_logic;
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wbs_adr_i: in std_logic_vector(27 downto 2);
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wbs_adr_i: in std_logic_vector(27 downto 2);
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wbs_dat_i: in std_logic_vector(31 downto 0);
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wbs_dat_i: in std_logic_vector(31 downto 0);
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wbs_dat_o: out std_logic_vector(31 downto 0);
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wbs_dat_o: out std_logic_vector(31 downto 0);
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elapsed_o: out std_logic
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elapsed_o: out std_logic
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);
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);
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end entity;
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end entity;
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architecture rtl of timer is
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architecture rtl of timer is
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signal pulses: unsigned(31 downto 0):=(others=>'0');
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signal pulses: unsigned(31 downto 0):=(others=>'0');
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signal interval: unsigned(31 downto 0):=(others=>'0');
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signal interval: unsigned(31 downto 0):=(others=>'0');
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signal cnt: unsigned(31 downto 0):=(others=>'0');
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signal cnt: unsigned(31 downto 0):=(others=>'0');
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signal elapsed: std_logic:='0';
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signal elapsed: std_logic:='0';
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begin
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begin
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process (clk_i) is
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process (clk_i) is
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begin
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begin
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if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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if rst_i='1' then
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if rst_i='1' then
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pulses<=(others=>'0');
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pulses<=(others=>'0');
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interval<=(others=>'0');
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interval<=(others=>'0');
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cnt<=(others=>'0');
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cnt<=(others=>'0');
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elapsed<='0';
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elapsed<='0';
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else
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else
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elapsed<='0';
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elapsed<='0';
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if pulses/=X"00000000" or cnt/=X"00000000" then
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if pulses/=X"00000000" or cnt/=X"00000000" then
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if cnt=X"00000000" then
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if cnt=X"00000000" then
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if pulses/=X"FFFFFFFF" then
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if pulses/=X"FFFFFFFF" then
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pulses<=pulses-1;
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pulses<=pulses-1;
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end if;
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end if;
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if pulses/=X"00000000" then
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if pulses/=X"00000000" then
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cnt<=interval;
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cnt<=interval;
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end if;
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end if;
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else
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else
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cnt<=cnt-1;
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cnt<=cnt-1;
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end if;
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end if;
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if cnt=X"00000001" then
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if cnt=X"00000001" then
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elapsed<='1';
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elapsed<='1';
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end if;
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end if;
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end if;
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end if;
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if wbs_cyc_i='1' and wbs_stb_i='1' and wbs_we_i='1' then
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if wbs_cyc_i='1' and wbs_stb_i='1' and wbs_we_i='1' then
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for i in wbs_sel_i'range loop
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for i in wbs_sel_i'range loop
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if wbs_sel_i(i)='1' then
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if wbs_sel_i(i)='1' then
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if wbs_adr_i="00"&X"000000" then
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if wbs_adr_i="00"&X"000000" then
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pulses(i*8+7 downto i*8)<=
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pulses(i*8+7 downto i*8)<=
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unsigned(wbs_dat_i(i*8+7 downto i*8));
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unsigned(wbs_dat_i(i*8+7 downto i*8));
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cnt<=(others=>'0');
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cnt<=(others=>'0');
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end if;
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end if;
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if wbs_adr_i="00"&X"000001" then
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if wbs_adr_i="00"&X"000001" then
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interval(i*8+7 downto i*8)<=
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interval(i*8+7 downto i*8)<=
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unsigned(wbs_dat_i(i*8+7 downto i*8));
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unsigned(wbs_dat_i(i*8+7 downto i*8));
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cnt<=(others=>'0');
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cnt<=(others=>'0');
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end if;
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end if;
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end if;
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end if;
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end loop;
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end loop;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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wbs_ack_o<=wbs_cyc_i and wbs_stb_i;
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wbs_ack_o<=wbs_cyc_i and wbs_stb_i;
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wbs_dat_o<=std_logic_vector(pulses) when wbs_adr_i="00"&X"000000" else
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wbs_dat_o<=std_logic_vector(pulses) when wbs_adr_i="00"&X"000000" else
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std_logic_vector(interval) when wbs_adr_i="00"&X"000001" else
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std_logic_vector(interval) when wbs_adr_i="00"&X"000001" else
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(others=>'-');
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(others=>'-');
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elapsed_o<=elapsed;
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elapsed_o<=elapsed;
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end architecture;
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end architecture;
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