---------------------------------------------------------------------
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---------------------------------------------------------------------
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-- LXP32 verification environment (self-checking testbench)
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-- LXP32 verification environment (self-checking testbench)
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--
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--
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-- Part of the LXP32 testbench
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-- Part of the LXP32 testbench
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--
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--
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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-- Copyright (c) 2016 by Alex I. Kuznetsov
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--
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--
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-- Simulates LXP32 test platform, verifies results.
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-- Simulates LXP32 test platform, verifies results.
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--
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--
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-- Parameters:
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-- Parameters:
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-- CPU_DBUS_RMW: DBUS_RMW CPU generic
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-- CPU_DBUS_RMW: DBUS_RMW CPU generic
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-- CPU_MUL_ARCH: MUL_ARCH CPU generic
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-- CPU_MUL_ARCH: MUL_ARCH CPU generic
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-- MODEL_LXP32C: when true, simulates LXP32C variant (with
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-- MODEL_LXP32C: when true, simulates LXP32C variant (with
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-- instruction cache), otherwise LXP32U
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-- instruction cache), otherwise LXP32U
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-- TEST_CASE: If non-empty, selects a test case to run.
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-- TEST_CASE: If non-empty, selects a test case to run.
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-- If empty, all tests are executed.
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-- If empty, all tests are executed.
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-- THROTTLE_IBUS: perform pseudo-random instruction bus
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-- THROTTLE_IBUS: perform pseudo-random instruction bus
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-- throttling
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-- throttling
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-- THROTTLE_DBUS: perform pseudo-random data bus throttling
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-- THROTTLE_DBUS: perform pseudo-random data bus throttling
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-- VERBOSE: report everything that is written to the
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-- VERBOSE: report everything that is written to the
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-- test monitor address space
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-- test monitor address space
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---------------------------------------------------------------------
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---------------------------------------------------------------------
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use std.textio.all;
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use std.textio.all;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use work.tb_pkg.all;
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use work.tb_pkg.all;
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entity tb is
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entity tb is
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generic(
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generic(
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CPU_DBUS_RMW: boolean:=false;
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CPU_DBUS_RMW: boolean:=false;
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CPU_MUL_ARCH: string:="dsp";
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CPU_MUL_ARCH: string:="dsp";
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MODEL_LXP32C: boolean:=true;
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MODEL_LXP32C: boolean:=true;
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TEST_CASE: string:="";
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TEST_CASE: string:="";
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THROTTLE_DBUS: boolean:=true;
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THROTTLE_DBUS: boolean:=true;
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THROTTLE_IBUS: boolean:=true;
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THROTTLE_IBUS: boolean:=true;
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VERBOSE: boolean:=false
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VERBOSE: boolean:=false
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);
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);
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end entity;
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end entity;
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architecture testbench of tb is
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architecture testbench of tb is
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signal clk: std_logic:='0';
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signal clk: std_logic:='0';
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signal globals: soc_globals_type:=(others=>'1');
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signal globals: soc_globals_type:=(others=>'1');
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signal soc_wbs_in: soc_wbs_in_type;
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signal soc_wbs_in: soc_wbs_in_type;
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signal soc_wbs_out: soc_wbs_out_type;
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signal soc_wbs_out: soc_wbs_out_type;
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signal soc_wbm_in: soc_wbm_in_type;
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signal soc_wbm_in: soc_wbm_in_type;
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signal soc_wbm_out: soc_wbm_out_type;
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signal soc_wbm_out: soc_wbm_out_type;
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|
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signal monitor_out: monitor_out_type;
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signal monitor_out: monitor_out_type;
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signal finish: std_logic:='0';
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signal finish: std_logic:='0';
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begin
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begin
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dut: entity work.platform(rtl)
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dut: entity work.platform(rtl)
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generic map(
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generic map(
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CPU_DBUS_RMW=>CPU_DBUS_RMW,
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CPU_DBUS_RMW=>CPU_DBUS_RMW,
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CPU_MUL_ARCH=>CPU_MUL_ARCH,
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CPU_MUL_ARCH=>CPU_MUL_ARCH,
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MODEL_LXP32C=>MODEL_LXP32C,
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MODEL_LXP32C=>MODEL_LXP32C,
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THROTTLE_DBUS=>THROTTLE_DBUS,
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THROTTLE_DBUS=>THROTTLE_DBUS,
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THROTTLE_IBUS=>THROTTLE_IBUS
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THROTTLE_IBUS=>THROTTLE_IBUS
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)
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)
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port map(
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port map(
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clk_i=>clk,
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clk_i=>clk,
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rst_i=>globals.rst_i,
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rst_i=>globals.rst_i,
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cpu_rst_i=>globals.cpu_rst_i,
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cpu_rst_i=>globals.cpu_rst_i,
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wbm_cyc_o=>soc_wbm_out.cyc,
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wbm_cyc_o=>soc_wbm_out.cyc,
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wbm_stb_o=>soc_wbm_out.stb,
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wbm_stb_o=>soc_wbm_out.stb,
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wbm_we_o=>soc_wbm_out.we,
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wbm_we_o=>soc_wbm_out.we,
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wbm_sel_o=>soc_wbm_out.sel,
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wbm_sel_o=>soc_wbm_out.sel,
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wbm_ack_i=>soc_wbm_in.ack,
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wbm_ack_i=>soc_wbm_in.ack,
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wbm_adr_o=>soc_wbm_out.adr,
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wbm_adr_o=>soc_wbm_out.adr,
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wbm_dat_o=>soc_wbm_out.dat,
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wbm_dat_o=>soc_wbm_out.dat,
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wbm_dat_i=>soc_wbm_in.dat,
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wbm_dat_i=>soc_wbm_in.dat,
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wbs_cyc_i=>soc_wbs_in.cyc,
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wbs_cyc_i=>soc_wbs_in.cyc,
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wbs_stb_i=>soc_wbs_in.stb,
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wbs_stb_i=>soc_wbs_in.stb,
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wbs_we_i=>soc_wbs_in.we,
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wbs_we_i=>soc_wbs_in.we,
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wbs_sel_i=>soc_wbs_in.sel,
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wbs_sel_i=>soc_wbs_in.sel,
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wbs_ack_o=>soc_wbs_out.ack,
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wbs_ack_o=>soc_wbs_out.ack,
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wbs_adr_i=>soc_wbs_in.adr,
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wbs_adr_i=>soc_wbs_in.adr,
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wbs_dat_i=>soc_wbs_in.dat,
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wbs_dat_i=>soc_wbs_in.dat,
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wbs_dat_o=>soc_wbs_out.dat
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wbs_dat_o=>soc_wbs_out.dat
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);
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);
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monitor_inst: entity work.monitor(sim)
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monitor_inst: entity work.monitor(sim)
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generic map(
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generic map(
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VERBOSE=>VERBOSE
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VERBOSE=>VERBOSE
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)
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)
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port map(
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port map(
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clk_i=>clk,
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clk_i=>clk,
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rst_i=>globals.rst_i,
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rst_i=>globals.rst_i,
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wbs_cyc_i=>soc_wbm_out.cyc,
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wbs_cyc_i=>soc_wbm_out.cyc,
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wbs_stb_i=>soc_wbm_out.stb,
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wbs_stb_i=>soc_wbm_out.stb,
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wbs_we_i=>soc_wbm_out.we,
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wbs_we_i=>soc_wbm_out.we,
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wbs_sel_i=>soc_wbm_out.sel,
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wbs_sel_i=>soc_wbm_out.sel,
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wbs_ack_o=>soc_wbm_in.ack,
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wbs_ack_o=>soc_wbm_in.ack,
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wbs_adr_i=>soc_wbm_out.adr,
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wbs_adr_i=>soc_wbm_out.adr,
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wbs_dat_i=>soc_wbm_out.dat,
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wbs_dat_i=>soc_wbm_out.dat,
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wbs_dat_o=>soc_wbm_in.dat,
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wbs_dat_o=>soc_wbm_in.dat,
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finished_o=>monitor_out.valid,
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finished_o=>monitor_out.valid,
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result_o=>monitor_out.data
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result_o=>monitor_out.data
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);
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);
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clk<=not clk and not finish after 5 ns;
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clk<=not clk and not finish after 5 ns;
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process is
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process is
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begin
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begin
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if TEST_CASE'length=0 then
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if TEST_CASE'length=0 then
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run_test("test001.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test001.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test002.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test002.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test003.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test003.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test004.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test004.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test005.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test005.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test006.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test006.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test007.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test007.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test008.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test008.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test009.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test009.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test010.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test010.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test011.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test011.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test012.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test012.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test013.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test013.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test014.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test014.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test015.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test015.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test016.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test016.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test017.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test017.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test018.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test018.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test019.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test019.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test020.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test("test020.ram",clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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else
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else
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run_test(TEST_CASE,clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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run_test(TEST_CASE,clk,globals,soc_wbs_in,soc_wbs_out,monitor_out);
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end if;
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end if;
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report "ALL TESTS WERE COMPLETED SUCCESSFULLY";
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report "ALL TESTS WERE COMPLETED SUCCESSFULLY";
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finish<='1';
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finish<='1';
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wait;
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wait;
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end process;
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end process;
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end architecture;
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end architecture;
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