URL
https://opencores.org/ocsvn/m1_core/m1_core/trunk
[/] [m1_core/] [trunk/] [doc/] [TODO.txt] - Diff between revs 62 and 64
Only display areas with differences |
Details |
Blame |
View Log
Rev 62 |
Rev 64 |
Simply RISC M1 Core ("Mistral") TODO List
|
M1 Core ("Mistral") TODO List
|
=========================================
|
=============================
|
|
|
Implementation
|
Implementation
|
--------------
|
--------------
|
At the moment the CPU has no exception nor external interrupt handling.
|
At the moment the CPU has no exception nor external interrupt handling.
|
|
|
|
|
Functional Verification
|
Functional Verification
|
-----------------------
|
-----------------------
|
Several simulations have been performed by Fabio Motta, Simone Lunardo and Paolo Piscopo.
|
Several simulations have been performed by Fabio Motta, Simone Lunardo and Paolo Piscopo.
|
|
|
|
|
Open issues
|
Open issues
|
-----------
|
-----------
|
- Jump are working (J JAL JR JALR) including the delay slot;
|
- Jump are working (J JAL JR JALR) including the delay slot;
|
- equality branches (BEQ BNE) executed 2 delay slots rather than just 1, should be correct now;
|
- equality branches (BEQ BNE) executed 2 delay slots rather than just 1, should be correct now;
|
- disequality branches (BLEZ BGTZ BLTZ BGEZ) do not work yet.
|
- disequality branches (BLEZ BGTZ BLTZ BGEZ) do not work yet.
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.