# Synthesis script for dc_shell (Tcl mode)
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# Synthesis script for dc_shell (Tcl mode)
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# Analyze
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# Analyze
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analyze -format verilog ~/m1_core/hdl/rtl/m1_core/m1_alu.v
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analyze -format verilog ~/m1_core/trunk/hdl/rtl/m1_core/trunk/m1_alu.v
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analyze -format verilog ~/m1_core/hdl/rtl/m1_core/m1_mul.v
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analyze -format verilog ~/m1_core/trunk/hdl/rtl/m1_core/trunk/m1_mul.v
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analyze -format verilog ~/m1_core/hdl/rtl/m1_core/m1_div.v
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analyze -format verilog ~/m1_core/trunk/hdl/rtl/m1_core/trunk/m1_div.v
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analyze -format verilog ~/m1_core/hdl/rtl/m1_core/m1_cpu.v
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analyze -format verilog ~/m1_core/trunk/hdl/rtl/m1_core/trunk/m1_cpu.v
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analyze -format verilog ~/m1_core/hdl/rtl/m1_core/m1_mmu.v
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analyze -format verilog ~/m1_core/trunk/hdl/rtl/m1_core/trunk/m1_mmu.v
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analyze -format verilog ~/m1_core/hdl/rtl/m1_core/m1_core.v
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analyze -format verilog ~/m1_core/trunk/hdl/rtl/m1_core/trunk/m1_core.v
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# Technology-independent elaboration and linking
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# Technology-independent elaboration and linking
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set active_design m1_core
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set active_design m1_core
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elaborate $active_design
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elaborate $active_design
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current_design $active_design
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current_design $active_design
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link
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link
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uniquify
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uniquify
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# Constraints and mapping on target library
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# Constraints and mapping on target library
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create_clock -period 4.0 -waveform [list 0 2.0] sys_clock_i
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create_clock -period 4.0 -waveform [list 0 2.0] sys_clock_i
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set_input_delay 2.0 -clock sys_clock_i -max [all_inputs]
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set_input_delay 2.0 -clock sys_clock_i -max [all_inputs]
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set_output_delay 1.0 -clock sys_clock_i -max [all_outputs]
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set_output_delay 1.0 -clock sys_clock_i -max [all_outputs]
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set_dont_touch_network [list sys_clock_i sys_reset_i]
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set_dont_touch_network [list sys_clock_i sys_reset_i]
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set_drive 0 [list sys_clock_i sys_reset_i]
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set_drive 0 [list sys_clock_i sys_reset_i]
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set_wire_load_mode enclosed
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set_wire_load_mode enclosed
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set_max_area 0
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set_max_area 0
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set_fix_multiple_port_nets -buffer_constants -all
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set_fix_multiple_port_nets -buffer_constants -all
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compile
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compile
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# Export the mapped design
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# Export the mapped design
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remove_unconnected_ports [find -hierarchy cell {"*"}]
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remove_unconnected_ports [find -hierarchy cell {"*"}]
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write -format ddc -hierarchy -output $active_design.ddc
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write -format ddc -hierarchy -output $active_design.ddc
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write -format verilog -hierarchy -output $active_design.sv
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write -format verilog -hierarchy -output $active_design.sv
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# Report area and timing
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# Report area and timing
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report_area -hierarchy > report_area.rpt
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report_area -hierarchy > report_area.rpt
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report_timing > report_timing.rpt
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report_timing > report_timing.rpt
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report_constraint -all_violators > report_constraint.rpt
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report_constraint -all_violators > report_constraint.rpt
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quit
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quit
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