/*
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/*
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* Simply RISC M1 Core Top-Level
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* Simply RISC M1 Core Top-Level
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*
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*
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* Schematic with instances of CPU, ALU, Mul, Div and MMU
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* Schematic with instances of CPU, ALU, Mul, Div and MMU
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*/
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*/
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module m1_core (
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module m1_core (
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// System
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// System
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input sys_clock_i, // System clock
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input sys_clock_i, // System clock
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input sys_reset_i, // System reset
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input sys_reset_i, // System reset
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input sys_irq_i, // Interrupt Request
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input sys_irq_i, // Interrupt Request
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// Wishbone master interface
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// Wishbone master interface
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output wb_cyc_o, // WB Cycle
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output wb_cyc_o, // WB Cycle
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output wb_stb_o, // WB Strobe
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output wb_stb_o, // WB Strobe
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output wb_we_o, // WB Write Enable
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output wb_we_o, // WB Write Enable
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output[31:0] wb_adr_o, // WB Address
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output[31:0] wb_adr_o, // WB Address
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output[31:0] wb_dat_o, // WB Data Out
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output[31:0] wb_dat_o, // WB Data Out
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output[3:0] wb_sel_o, // WB Byte Select
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output[3:0] wb_sel_o, // WB Byte Select
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input wb_ack_i, // WB Ack
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input wb_ack_i, // WB Ack
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input[31:0] wb_dat_i // WB Data In
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input[31:0] wb_dat_i // WB Data In
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);
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);
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/*
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/*
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* Wires
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* Wires
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*/
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*/
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// ALU
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// ALU
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wire[31:0] alu_a;
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wire[31:0] alu_a;
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wire[31:0] alu_b;
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wire[31:0] alu_b;
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wire[4:0] alu_func;
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wire[4:0] alu_func;
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wire alu_signed;
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wire alu_signed;
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wire[32:0] alu_result;
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wire[32:0] alu_result;
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// Multiplier
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// Multiplier
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wire mul_req;
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wire mul_req;
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wire[31:0] mul_a;
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wire[31:0] mul_a;
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wire[31:0] mul_b;
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wire[31:0] mul_b;
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wire mul_signed;
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wire mul_signed;
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wire mul_ack;
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wire mul_ack;
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wire[63:0] mul_product;
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wire[63:0] mul_product;
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// Divider
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// Divider
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wire div_req;
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wire div_req;
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wire[31:0] div_a;
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wire[31:0] div_a;
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wire[31:0] div_b;
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wire[31:0] div_b;
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wire div_signed;
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wire div_signed;
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wire div_ack;
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wire div_ack;
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wire[31:0] div_quotient;
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wire[31:0] div_quotient;
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wire[31:0] div_remainder;
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wire[31:0] div_remainder;
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// Instruction Memory
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// Instruction Memory
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wire imem_read;
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wire imem_read;
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wire[31:0] imem_addr;
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wire[31:0] imem_addr;
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wire imem_done;
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wire imem_done;
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wire[31:0] imem_data;
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wire[31:0] imem_data;
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// Data Memory
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// Data Memory
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wire dmem_read;
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wire dmem_read;
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wire dmem_write;
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wire dmem_write;
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wire[31:0] dmem_addr;
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wire[31:0] dmem_addr;
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wire[31:0] dmem_data_w;
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wire[31:0] dmem_data_w;
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wire[3:0] dmem_sel;
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wire[3:0] dmem_sel;
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wire dmem_done;
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wire dmem_done;
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wire[31:0] dmem_data_r;
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wire[31:0] dmem_data_r;
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/*
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/*
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* Module instances
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* Module instances
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*/
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*/
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// CPU
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// CPU
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m1_cpu m1_cpu_0 (
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m1_cpu m1_cpu_0 (
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// System
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// System
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.sys_clock_i(sys_clock_i),
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.sys_clock_i(sys_clock_i),
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.sys_reset_i(sys_reset_i),
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.sys_reset_i(sys_reset_i),
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.sys_irq_i(sys_irq_i),
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.sys_irq_i(sys_irq_i),
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// ALU
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// ALU
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.alu_a_o(alu_a),
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.alu_a_o(alu_a),
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.alu_b_o(alu_b),
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.alu_b_o(alu_b),
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.alu_func_o(alu_func),
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.alu_func_o(alu_func),
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.alu_signed_o(alu_signed),
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.alu_signed_o(alu_signed),
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.alu_result_i(alu_result),
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.alu_result_i(alu_result),
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// Multiplier
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// Multiplier
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.mul_req_o(mul_req),
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.mul_req_o(mul_req),
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.mul_a_o(mul_a),
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.mul_a_o(mul_a),
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.mul_b_o(mul_b),
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.mul_b_o(mul_b),
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.mul_signed_o(mul_signed),
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.mul_signed_o(mul_signed),
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.mul_ack_i(mul_ack),
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.mul_ack_i(mul_ack),
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.mul_product_i(mul_product),
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.mul_product_i(mul_product),
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// Divider
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// Divider
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.div_req_o(div_req),
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.div_req_o(div_req),
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.div_a_o(div_a),
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.div_a_o(div_a),
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.div_b_o(div_b),
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.div_b_o(div_b),
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.div_signed_o(div_signed),
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.div_signed_o(div_signed),
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.div_ack_i(div_ack),
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.div_ack_i(div_ack),
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.div_quotient_i(div_quotient),
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.div_quotient_i(div_quotient),
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.div_remainder_i(div_remainder),
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.div_remainder_i(div_remainder),
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// Instruction Memory
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// Instruction Memory
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.imem_read_o(imem_read),
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.imem_read_o(imem_read),
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.imem_addr_o(imem_addr),
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.imem_addr_o(imem_addr),
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.imem_data_i(imem_data),
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.imem_data_i(imem_data),
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.imem_done_i(imem_done),
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.imem_done_i(imem_done),
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// Data Memory
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// Data Memory
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.dmem_read_o(dmem_read),
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.dmem_read_o(dmem_read),
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.dmem_write_o(dmem_write),
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.dmem_write_o(dmem_write),
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.dmem_sel_o(dmem_sel),
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.dmem_sel_o(dmem_sel),
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.dmem_addr_o(dmem_addr),
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.dmem_addr_o(dmem_addr),
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.dmem_data_o(dmem_data_w),
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.dmem_data_o(dmem_data_w),
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.dmem_data_i(dmem_data_r),
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.dmem_data_i(dmem_data_r),
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.dmem_done_i(dmem_done)
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.dmem_done_i(dmem_done)
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);
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);
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// ALU
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// ALU
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m1_alu m1_alu_0 (
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m1_alu m1_alu_0 (
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.a_i(alu_a),
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.a_i(alu_a),
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.b_i(alu_b),
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.b_i(alu_b),
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.func_i(alu_func),
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.func_i(alu_func),
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.signed_i(alu_signed),
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.signed_i(alu_signed),
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.result_o(alu_result)
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.result_o(alu_result)
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);
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);
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// Multiplier
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// Multiplier
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m1_mul m1_mul_0 (
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m1_mul m1_mul_0 (
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.sys_reset_i(sys_reset_i),
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.sys_reset_i(sys_reset_i),
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.sys_clock_i(sys_clock_i),
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.sys_clock_i(sys_clock_i),
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.abp_req_i(mul_req),
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.abp_req_i(mul_req),
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.a_i(mul_a),
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.a_i(mul_a),
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.b_i(mul_b),
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.b_i(mul_b),
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.signed_i(mul_signed),
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.signed_i(mul_signed),
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.abp_ack_o(mul_ack),
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.abp_ack_o(mul_ack),
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.product_o(mul_product)
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.product_o(mul_product)
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);
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);
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// Divider
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// Divider
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m1_div m1_div_0 (
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m1_div m1_div_0 (
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.sys_reset_i(sys_reset_i),
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.sys_reset_i(sys_reset_i),
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.sys_clock_i(sys_clock_i),
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.sys_clock_i(sys_clock_i),
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.abp_req_i(div_req),
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.abp_req_i(div_req),
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.a_i(div_a),
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.a_i(div_a),
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.b_i(div_b),
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.b_i(div_b),
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.signed_i(div_signed),
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.signed_i(div_signed),
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.abp_ack_o(div_ack),
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.abp_ack_o(div_ack),
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.quotient_o(div_quotient),
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.quotient_o(div_quotient),
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.remainder_o(div_remainder)
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.remainder_o(div_remainder)
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);
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);
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// MMU
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// MMU
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m1_mmu m1_mmu_0 (
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m1_mmu m1_mmu_0 (
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// System
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// System
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.sys_clock_i(sys_clock_i),
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.sys_clock_i(sys_clock_i),
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.sys_reset_i(sys_reset_i),
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.sys_reset_i(sys_reset_i),
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// Instruction Memory
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// Instruction Memory
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.imem_read_i(imem_read),
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.imem_read_i(imem_read),
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.imem_addr_i(imem_addr),
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.imem_addr_i(imem_addr),
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.imem_data_o(imem_data),
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.imem_data_o(imem_data),
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.imem_done_o(imem_done),
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.imem_done_o(imem_done),
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// Data Memory
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// Data Memory
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.dmem_read_i(dmem_read),
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.dmem_read_i(dmem_read),
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.dmem_write_i(dmem_write),
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.dmem_write_i(dmem_write),
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.dmem_sel_i(dmem_sel),
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.dmem_sel_i(dmem_sel),
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.dmem_addr_i(dmem_addr),
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.dmem_addr_i(dmem_addr),
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.dmem_data_i(dmem_data_w),
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.dmem_data_i(dmem_data_w),
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.dmem_data_o(dmem_data_r),
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.dmem_data_o(dmem_data_r),
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.dmem_done_o(dmem_done),
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.dmem_done_o(dmem_done),
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// Wishbone master interface
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// Wishbone master interface
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.wb_cyc_o(wb_cyc_o),
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.wb_cyc_o(wb_cyc_o),
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.wb_stb_o(wb_stb_o),
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.wb_stb_o(wb_stb_o),
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.wb_we_o(wb_we_o),
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.wb_we_o(wb_we_o),
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.wb_adr_o(wb_adr_o),
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.wb_adr_o(wb_adr_o),
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.wb_dat_o(wb_dat_o),
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.wb_dat_o(wb_dat_o),
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.wb_sel_o(wb_sel_o),
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.wb_sel_o(wb_sel_o),
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.wb_ack_i(wb_ack_i),
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.wb_ack_i(wb_ack_i),
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.wb_dat_i(wb_dat_i)
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.wb_dat_i(wb_dat_i)
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);
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);
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endmodule
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endmodule
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