// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: ADDR_UNIT.v
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// Filename: ADDR_UNIT.v
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// Version: 1.0
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// Version: 1.1 bug fix
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// Date: 30 May 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 7 October 2015
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2015 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// ADDR_UNIT generates data access addresses and controls data cache operation
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// ADDR_UNIT generates data access addresses and controls data cache operation
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD,
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module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD,
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DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17,
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DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17,
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NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, REG_OUT, BITSEL );
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NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, REG_OUT, BITSEL,
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QWATWO );
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input BCLK,BRESET;
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input BCLK,BRESET;
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input READ,WRITE,LDEA;
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input READ,WRITE,LDEA;
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input NEWACC;
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input NEWACC;
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input CLRMSW,POST,FULLACC;
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input CLRMSW,POST,FULLACC;
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input [1:0] SRC2SEL;
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input [1:0] SRC2SEL;
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input [3:0] INDEX;
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input [3:0] INDEX;
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input [1:0] ASIZE;
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input [1:0] ASIZE;
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input [31:0] SRC1,SRC2;
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input [31:0] SRC1,SRC2;
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input [1:0] BWD;
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input [1:0] BWD;
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input [31:0] DISP;
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input [31:0] DISP;
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input [31:0] PC_ARCHI,PC_ICACHE;
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input [31:0] PC_ARCHI,PC_ICACHE;
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input DISP_OK;
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input DISP_OK;
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input IO_READY;
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input IO_READY;
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input [5:0] ACC_STAT; // Feedback from data cache about the running access
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input [5:0] ACC_STAT; // Feedback from data cache about the running access
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input [1:0] MMU_UPDATE;
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input [1:0] MMU_UPDATE;
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input [2:0] IC_TEX;
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input [2:0] IC_TEX;
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input [1:0] ABO_STAT;
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input [1:0] ABO_STAT;
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input ADIVAR;
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input ADIVAR;
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input RWVAL_1; // special access for RDVAL + WRVAL
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input RWVAL_1; // special access for RDVAL + WRVAL
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input OP_RMW;
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input OP_RMW;
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input PHASE_17;
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input PHASE_17;
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input NO_TRAP;
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input NO_TRAP;
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input FPU_TRAP;
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input FPU_TRAP;
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output READ_OUT,WRITE_OUT,ZTEST,RMW;
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output READ_OUT,WRITE_OUT,ZTEST,RMW;
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output [31:0] VADR;
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output [31:0] VADR;
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output [31:0] ADDR;
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output [31:0] ADDR;
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output [1:0] SIZE;
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output [1:0] SIZE;
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output [3:0] PACKET;
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output [3:0] PACKET;
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output ACC_DONE;
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output ACC_DONE;
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output ABORT;
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output ABORT;
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output REG_OUT;
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output REG_OUT;
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output [2:0] BITSEL;
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output [2:0] BITSEL;
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output reg QWATWO;
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reg [31:0] VADR;
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reg [31:0] VADR;
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reg READ_OUT,write_reg,ZTEST,RMW;
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reg READ_OUT,write_reg,ZTEST,RMW;
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reg [1:0] SIZE;
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reg [1:0] SIZE;
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reg [3:0] PACKET;
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reg [3:0] PACKET;
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reg [2:0] BITSEL;
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reg [2:0] BITSEL;
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reg [31:0] source2;
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reg [31:0] source2;
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reg [31:0] index_val;
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reg [31:0] index_val;
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reg [31:0] vadr_reg;
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reg [31:0] vadr_reg;
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reg [31:0] ea_reg;
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reg [31:0] ea_reg;
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reg [31:0] tos_offset;
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reg [31:0] tos_offset;
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reg [31:0] icache_adr;
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reg [31:0] icache_adr;
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reg [31:0] sign_ext_src1;
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reg [31:0] sign_ext_src1;
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reg [31:12] pg_areg;
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reg [31:12] pg_areg;
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reg reg_out_i,next_reg;
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reg reg_out_i,next_reg;
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reg ld_ea_reg;
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reg ld_ea_reg;
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reg acc_run,acc_ende,acc_step;
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reg acc_run,acc_ende,acc_step;
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reg qwa_flag;
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reg qwa_flag;
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reg no_done;
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reg no_done;
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reg frueh_ok;
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reg frueh_ok;
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reg io_rdy;
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reg io_rdy;
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reg ABORT;
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reg ABORT;
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reg [1:0] tex_feld;
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reg [1:0] tex_feld;
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reg [2:0] u_ddt;
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reg [2:0] u_ddt;
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reg pg_op;
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reg pg_op;
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reg do_wr;
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reg do_wr;
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wire acc_ok,acc_err,io_acc;
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wire acc_ok,acc_err,io_acc;
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wire acc_pass;
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wire acc_pass;
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wire ca_hit;
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wire ca_hit;
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wire [31:0] reg_adder;
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wire [31:0] reg_adder;
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wire [31:0] next_vadr;
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wire [31:0] next_vadr;
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wire [31:0] final_addr;
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wire [31:0] final_addr;
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wire [31:0] pg_addr;
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wire [31:0] pg_addr;
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wire [1:0] inc_pack;
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wire [1:0] inc_pack;
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wire [3:0] index_sel;
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wire [3:0] index_sel;
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wire ld_ea_i;
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wire ld_ea_i;
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wire ea_ok;
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wire ea_ok;
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wire qw_align;
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wire qw_align;
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wire init_acc;
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wire init_acc;
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wire in_page;
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wire in_page;
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wire all_ok;
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wire all_ok;
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wire fa_out;
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wire fa_out;
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wire pg_test;
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wire pg_test;
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// ++++++++++++++++++++ Decoding ACC_STAT from data cache ++++++++++++++++++++++++++++
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// ++++++++++++++++++++ Decoding ACC_STAT from data cache ++++++++++++++++++++++++++++
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// ACC_STAT[5:0] : CA_HIT, IO_ACC, PROT_ERROR , ABO_LEVEL1 , ABORT , ACC_OK
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// ACC_STAT[5:0] : CA_HIT, IO_ACC, PROT_ERROR , ABO_LEVEL1 , ABORT , ACC_OK
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assign ca_hit = ACC_STAT[5];
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assign ca_hit = ACC_STAT[5];
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assign io_acc = ACC_STAT[4];
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assign io_acc = ACC_STAT[4];
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assign acc_err = ACC_STAT[3] | ACC_STAT[1]; // Abort or Protection Error
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assign acc_err = ACC_STAT[3] | ACC_STAT[1]; // Abort or Protection Error
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assign acc_ok = ACC_STAT[0] & ~pg_op;
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assign acc_ok = ACC_STAT[0] & ~pg_op;
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assign acc_pass = ACC_STAT[0] & ZTEST;
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assign acc_pass = ACC_STAT[0] & ZTEST;
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always @(posedge BCLK) ABORT <= acc_err; // Signal to Steuerung - only a pulse
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always @(posedge BCLK) ABORT <= acc_err; // Signal to Steuerung - only a pulse
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always @(posedge BCLK) if (acc_err) tex_feld <= ACC_STAT[3] ? 2'b11 : {~ACC_STAT[2],ACC_STAT[2]}; // for MSR
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always @(posedge BCLK) if (acc_err) tex_feld <= ACC_STAT[3] ? 2'b11 : {~ACC_STAT[2],ACC_STAT[2]}; // for MSR
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always @(posedge BCLK) if (acc_err) u_ddt <= {RMW,ABO_STAT[1],(WRITE_OUT | ZTEST)};
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always @(posedge BCLK) if (acc_err) u_ddt <= {RMW,ABO_STAT[1],(WRITE_OUT | ZTEST)};
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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always @(SRC2SEL or CLRMSW or SRC2 or PC_ARCHI or ea_reg)
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always @(SRC2SEL or CLRMSW or SRC2 or PC_ARCHI or ea_reg)
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case (SRC2SEL)
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case (SRC2SEL)
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2'b00 : source2 = {(CLRMSW ? 16'h0000 : SRC2[31:16]),SRC2[15:0]}; // base reg, External Addressing with MOD
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2'b00 : source2 = {(CLRMSW ? 16'h0000 : SRC2[31:16]),SRC2[15:0]}; // base reg, External Addressing with MOD
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2'b01 : source2 = PC_ARCHI; // PC relative
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2'b01 : source2 = PC_ARCHI; // PC relative
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2'b10 : source2 = 32'h0; // Absolute Addressing
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2'b10 : source2 = 32'h0; // Absolute Addressing
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2'b11 : source2 = ea_reg; // REUSE : 2. TOS
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2'b11 : source2 = ea_reg; // REUSE : 2. TOS
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endcase
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endcase
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assign index_sel = POST ? 4'h0 : INDEX; // Alternative application of Index for POST Adder : POP from Stack
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assign index_sel = POST ? 4'h0 : INDEX; // Alternative application of Index for POST Adder : POP from Stack
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always @(BWD or SRC1)
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always @(BWD or SRC1)
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casex (BWD)
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casex (BWD)
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2'b00 : sign_ext_src1 = {{24{SRC1[7]}}, SRC1[7:0]}; // Byte
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2'b00 : sign_ext_src1 = {{24{SRC1[7]}}, SRC1[7:0]}; // Byte
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2'b01 : sign_ext_src1 = {{16{SRC1[15]}},SRC1[15:0]}; // Word
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2'b01 : sign_ext_src1 = {{16{SRC1[15]}},SRC1[15:0]}; // Word
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default : sign_ext_src1 = SRC1;
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default : sign_ext_src1 = SRC1;
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endcase
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endcase
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always @(index_sel or sign_ext_src1 or SRC1)
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always @(index_sel or sign_ext_src1 or SRC1)
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casex (index_sel)
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casex (index_sel)
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4'b1_0xx : index_val = sign_ext_src1; // für CASE
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4'b1_0xx : index_val = sign_ext_src1; // für CASE
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4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
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4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
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4'b0_100 : index_val = SRC1;
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4'b0_100 : index_val = SRC1;
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4'b0_101 : index_val = {SRC1[30:0],1'b0};
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4'b0_101 : index_val = {SRC1[30:0],1'b0};
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4'b0_110 : index_val = {SRC1[29:0],2'b00};
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4'b0_110 : index_val = {SRC1[29:0],2'b00};
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4'b0_111 : index_val = {SRC1[28:0],3'b000};
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4'b0_111 : index_val = {SRC1[28:0],3'b000};
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default : index_val = 32'h0;
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default : index_val = 32'h0;
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endcase
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endcase
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assign reg_adder = source2 + index_val; // SRC2 allows simple MOV with SRC1
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assign reg_adder = source2 + index_val; // SRC2 allows simple MOV with SRC1
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assign final_addr = reg_adder + DISP; // That's the final access address
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assign final_addr = reg_adder + DISP; // That's the final access address
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always @(posedge BCLK) if (LDEA && (index_sel[3:2] == 2'b11)) BITSEL <= SRC1[2:0]; // for Bit Opcodes in I_PFAD
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always @(posedge BCLK) if (LDEA && (index_sel[3:2] == 2'b11)) BITSEL <= SRC1[2:0]; // for Bit Opcodes in I_PFAD
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always @(INDEX) // SP POP Operation & String Backward
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always @(INDEX) // SP POP Operation & String Backward
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case (INDEX[2:0])
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case (INDEX[2:0])
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3'b000 : tos_offset = 32'h0000_0001;
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3'b000 : tos_offset = 32'h0000_0001;
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3'b001 : tos_offset = 32'h0000_0002;
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3'b001 : tos_offset = 32'h0000_0002;
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3'b010 : tos_offset = 32'h0000_0004;
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3'b010 : tos_offset = 32'h0000_0004;
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3'b011 : tos_offset = 32'h0000_0008;
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3'b011 : tos_offset = 32'h0000_0008;
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3'b100 : tos_offset = 32'hFFFF_FFFF;
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3'b100 : tos_offset = 32'hFFFF_FFFF;
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3'b101 : tos_offset = 32'hFFFF_FFFE;
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3'b101 : tos_offset = 32'hFFFF_FFFE;
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3'b110 : tos_offset = 32'hFFFF_FFFC;
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3'b110 : tos_offset = 32'hFFFF_FFFC;
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3'b111 : tos_offset = 32'hFFFF_FFF8;
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3'b111 : tos_offset = 32'hFFFF_FFF8;
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endcase
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endcase
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) ld_ea_reg <= 1'b0;
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if (!BRESET) ld_ea_reg <= 1'b0;
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else ld_ea_reg <= (LDEA | ld_ea_reg) & ~DISP_OK;
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else ld_ea_reg <= (LDEA | ld_ea_reg) & ~DISP_OK;
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assign ld_ea_i = (LDEA | ld_ea_reg) & DISP_OK;
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assign ld_ea_i = (LDEA | ld_ea_reg) & DISP_OK;
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assign ea_ok = (READ | WRITE | LDEA | ld_ea_reg) & ~FULLACC & DISP_OK;
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assign ea_ok = (READ | WRITE | LDEA | ld_ea_reg) & ~FULLACC & DISP_OK;
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always @(posedge BCLK) icache_adr <= PC_ICACHE;
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always @(posedge BCLK) icache_adr <= PC_ICACHE;
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// Memory for the calculated address for reuse and Register for POST modified addresses :
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// Memory for the calculated address for reuse and Register for POST modified addresses :
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (ld_ea_i)
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if (ld_ea_i)
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begin
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begin
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casex ({MMU_UPDATE[1],INDEX[0],POST})
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casex ({MMU_UPDATE[1],INDEX[0],POST})
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3'b10x : ea_reg <= MMU_UPDATE[0] ? vadr_reg : icache_adr; // TEAR
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3'b10x : ea_reg <= MMU_UPDATE[0] ? vadr_reg : icache_adr; // TEAR
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3'b11x : ea_reg <= MMU_UPDATE[0] ?
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3'b11x : ea_reg <= MMU_UPDATE[0] ?
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{24'h0000_00,3'b101, u_ddt, tex_feld} // MSR
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{24'h0000_00,3'b101, u_ddt, tex_feld} // MSR
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: {24'h0000_00,3'b100,IC_TEX[2],ABO_STAT[0],1'b0,IC_TEX[1:0]}; // only READ from ICACHE
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: {24'h0000_00,3'b100,IC_TEX[2],ABO_STAT[0],1'b0,IC_TEX[1:0]}; // only READ from ICACHE
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3'b0x1 : ea_reg <= source2 + tos_offset ;
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3'b0x1 : ea_reg <= source2 + tos_offset ;
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3'b0x0 : ea_reg <= final_addr;
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3'b0x0 : ea_reg <= final_addr;
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endcase
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endcase
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end
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end
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assign ADDR = ea_reg; // used for ADDR opcode and TOS Addressing
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assign ADDR = ea_reg; // used for ADDR opcode and TOS Addressing
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// This pulse stores all parameters of access
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// This pulse stores all parameters of access
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assign init_acc = ((FULLACC ? (NEWACC & acc_ende) : acc_ende) | ~acc_run) & DISP_OK & (READ | WRITE) & ~ABORT & NO_TRAP;
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assign init_acc = ((FULLACC ? (NEWACC & acc_ende) : acc_ende) | ~acc_run) & DISP_OK & (READ | WRITE) & ~ABORT & NO_TRAP;
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assign fa_out = init_acc | ADIVAR; // special case for LMR IVAR,...
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assign fa_out = init_acc | ADIVAR; // special case for LMR IVAR,...
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always @(fa_out or acc_ok or final_addr or qw_align or pg_op or pg_areg or vadr_reg or next_vadr)
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always @(fa_out or acc_ok or final_addr or qw_align or pg_op or pg_areg or vadr_reg or next_vadr)
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casex ({fa_out,acc_ok})
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casex ({fa_out,acc_ok})
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2'b1x : VADR = {final_addr[31:3],(final_addr[2] | qw_align),final_addr[1:0]};
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2'b1x : VADR = {final_addr[31:3],(final_addr[2] | qw_align),final_addr[1:0]};
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2'b00 : VADR = pg_op ? {pg_areg,12'h0} : vadr_reg;
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2'b00 : VADR = pg_op ? {pg_areg,12'h0} : vadr_reg;
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2'b01 : VADR = next_vadr;
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2'b01 : VADR = next_vadr;
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endcase
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endcase
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (init_acc) vadr_reg <= {final_addr[31:3],(final_addr[2] | qw_align),final_addr[1:0]};
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if (init_acc) vadr_reg <= {final_addr[31:3],(final_addr[2] | qw_align),final_addr[1:0]};
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else
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else
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if (pg_op && ZTEST && acc_err) vadr_reg <= {pg_areg,12'h0}; // for TEAR !
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if (pg_op && ZTEST && acc_err) vadr_reg <= {pg_areg,12'h0}; // for TEAR !
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else
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else
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if (acc_ok) vadr_reg <= next_vadr;
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if (acc_ok) vadr_reg <= next_vadr;
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assign next_vadr = qwa_flag ? {vadr_reg[31:3],3'b000} : ({vadr_reg[31:2],2'b00} + 32'h0000_0004);
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assign next_vadr = qwa_flag ? {vadr_reg[31:3],3'b000} : ({vadr_reg[31:2],2'b00} + 32'h0000_0004);
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// Logic for Page border WRITE Test
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// Logic for Page border WRITE Test
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assign pg_addr = final_addr + {29'h0,(ASIZE[1] & ASIZE[0]),ASIZE[1],(ASIZE[1] | ASIZE[0])};
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assign pg_addr = final_addr + {29'h0,(ASIZE[1] & ASIZE[0]),ASIZE[1],(ASIZE[1] | ASIZE[0])};
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always @(posedge BCLK) if (init_acc) pg_areg <= pg_addr[31:12];
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always @(posedge BCLK) if (init_acc) pg_areg <= pg_addr[31:12];
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assign pg_test = (final_addr[12] != pg_addr[12]) & ~OP_RMW; // At RMW no Test necessary
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assign pg_test = (final_addr[12] != pg_addr[12]) & ~OP_RMW; // At RMW no Test necessary
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) pg_op <= 1'b0;
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if (!BRESET) pg_op <= 1'b0;
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else
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else
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pg_op <= init_acc ? (WRITE & ~RWVAL_1 & pg_test) : (pg_op & ~acc_pass & ~acc_err);
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pg_op <= init_acc ? (WRITE & ~RWVAL_1 & pg_test) : (pg_op & ~acc_pass & ~acc_err);
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always @(posedge BCLK) do_wr <= pg_op & ZTEST & acc_pass; // All ok, Page exists => continue
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always @(posedge BCLK) do_wr <= pg_op & ZTEST & acc_pass; // All ok, Page exists => continue
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|
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) READ_OUT <= 1'b0;
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if (!BRESET) READ_OUT <= 1'b0;
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else
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else
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READ_OUT <= init_acc ? (READ & ~RWVAL_1) : (READ_OUT & ~acc_ende & ~acc_err);
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READ_OUT <= init_acc ? (READ & ~RWVAL_1) : (READ_OUT & ~acc_ende & ~acc_err);
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) write_reg <= 1'b0;
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if (!BRESET) write_reg <= 1'b0;
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else
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else
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write_reg <= (init_acc ? (WRITE & ~RWVAL_1 & ~pg_test) : (write_reg & ~acc_ende & ~acc_err & ~FPU_TRAP)) | do_wr;
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write_reg <= (init_acc ? (WRITE & ~RWVAL_1 & ~pg_test) : (write_reg & ~acc_ende & ~acc_err & ~FPU_TRAP)) | do_wr;
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assign WRITE_OUT = write_reg & ~FPU_TRAP;
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assign WRITE_OUT = write_reg & ~FPU_TRAP;
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// Special case for RDVAL and WRVAL
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// Special case for RDVAL and WRVAL
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) ZTEST <= 1'b0;
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if (!BRESET) ZTEST <= 1'b0;
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else
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else
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ZTEST <= pg_op ? (~ZTEST | (~acc_pass & ~acc_err)) : (init_acc ? RWVAL_1 : (ZTEST & ~acc_ende & ~acc_err));
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ZTEST <= pg_op ? (~ZTEST | (~acc_pass & ~acc_err)) : (init_acc ? RWVAL_1 : (ZTEST & ~acc_ende & ~acc_err));
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|
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) RMW <= 1'b0;
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if (!BRESET) RMW <= 1'b0;
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else
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else
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RMW <= init_acc ? (OP_RMW & PHASE_17) : (RMW & ~acc_ende & ~acc_err);
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RMW <= init_acc ? (OP_RMW & PHASE_17) : (RMW & ~acc_ende & ~acc_err);
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|
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// Special case : first MSD access by aligned QWORD READ
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// Special case : first MSD access by aligned QWORD READ
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assign qw_align = (final_addr[2:0] == 3'b000) & READ & (ASIZE == 2'b11);
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assign qw_align = (final_addr[2:0] == 3'b000) & READ & (ASIZE == 2'b11);
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|
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always @(posedge BCLK) if (init_acc) qwa_flag <= qw_align;
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always @(posedge BCLK) if (init_acc) qwa_flag <= qw_align;
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|
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always @(posedge BCLK or negedge BRESET) // central flag that shows the ADDR_UNIT is busy
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always @(posedge BCLK or negedge BRESET) // central flag that shows the ADDR_UNIT is busy
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if (!BRESET) acc_run <= 1'b0;
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if (!BRESET) acc_run <= 1'b0;
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else
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else
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acc_run <= init_acc | (acc_run & ~acc_ende & ~acc_err & ~FPU_TRAP);
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acc_run <= init_acc | (acc_run & ~acc_ende & ~acc_err & ~FPU_TRAP);
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|
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always @(posedge BCLK) if (init_acc) SIZE <= ASIZE;
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always @(posedge BCLK) if (init_acc) SIZE <= ASIZE;
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|
|
assign inc_pack = (PACKET[1:0] == 2'b00) ? 2'b10 : {(SIZE[1] ^ SIZE[0]),(SIZE[1] & SIZE[0])};
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assign inc_pack = (PACKET[1:0] == 2'b00) ? 2'b10 : {(SIZE[1] ^ SIZE[0]),(SIZE[1] & SIZE[0])};
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|
|
// Counter for data packets 1 to 3 : special case aligned QWORD : only 2 packets. Additionally start address in bits 1 und 0.
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// Counter for data packets 1 to 3 : special case aligned QWORD : only 2 packets. Additionally start address in bits 1 und 0.
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// special coding (00) -> [01] -> (10) , [01] optional by QWORD and (10) shows always the end
|
// special coding (00) -> [01] -> (10) , [01] optional by QWORD and (10) shows always the end
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always @(posedge BCLK)
|
always @(posedge BCLK)
|
if (init_acc) PACKET <= {2'b00,final_addr[1:0]};
|
if (init_acc) PACKET <= {2'b00,final_addr[1:0]};
|
else
|
else
|
if (acc_ok) PACKET <= PACKET + {inc_pack,2'b00};
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if (acc_ok) PACKET <= PACKET + {inc_pack,2'b00};
|
|
|
// This signal is the End signal for the ADDR_UNIT internally.
|
// This signal is the End signal for the ADDR_UNIT internally.
|
always @(SIZE or PACKET or acc_ok)
|
always @(SIZE or PACKET or acc_ok)
|
casex ({SIZE,PACKET[3],PACKET[1:0]})
|
casex ({SIZE,PACKET[3],PACKET[1:0]})
|
5'b00_x_xx : acc_ende = acc_ok; // Byte
|
5'b00_x_xx : acc_ende = acc_ok; // Byte
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5'b01_0_0x : acc_ende = acc_ok; // Word 1 packet
|
5'b01_0_0x : acc_ende = acc_ok; // Word 1 packet
|
5'b01_0_10 : acc_ende = acc_ok; // 1 packet
|
5'b01_0_10 : acc_ende = acc_ok; // 1 packet
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5'b01_1_xx : acc_ende = acc_ok; // 2 packets
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5'b01_1_xx : acc_ende = acc_ok; // 2 packets
|
5'b10_0_00 : acc_ende = acc_ok; // DWord 1 packet
|
5'b10_0_00 : acc_ende = acc_ok; // DWord 1 packet
|
5'b10_1_xx : acc_ende = acc_ok; // 2 packets
|
5'b10_1_xx : acc_ende = acc_ok; // 2 packets
|
5'b11_1_xx : acc_ende = acc_ok; // QWord at least 2 packets
|
5'b11_1_xx : acc_ende = acc_ok; // QWord at least 2 packets
|
default : acc_ende = 1'b0;
|
default : acc_ende = 1'b0;
|
endcase
|
endcase
|
|
|
assign in_page = (vadr_reg[11:3] != 9'h1FF); // Access inside a page ? During WRITE address is increasing : 1. LSD 2. MSD
|
assign in_page = (vadr_reg[11:3] != 9'h1FF); // Access inside a page ? During WRITE address is increasing : 1. LSD 2. MSD
|
|
|
always @(SIZE or vadr_reg or in_page or PACKET)
|
always @(SIZE or vadr_reg or in_page or PACKET)
|
casex (SIZE)
|
casex (SIZE)
|
2'b01 : frueh_ok = (vadr_reg[3:2] != 2'b11); //Word
|
2'b01 : frueh_ok = (vadr_reg[3:2] != 2'b11); //Word
|
2'b10 : frueh_ok = (vadr_reg[3:2] != 2'b11); //DWord
|
2'b10 : frueh_ok = (vadr_reg[3:2] != 2'b11); //DWord
|
2'b11 : frueh_ok = (PACKET[1:0] == 2'b00) ? (~vadr_reg[3] | ~vadr_reg[2]) : ((PACKET[3:2] == 2'b01) & (vadr_reg[3:2] != 2'b11));
|
2'b11 : frueh_ok = (PACKET[1:0] == 2'b00) ? (~vadr_reg[3] | ~vadr_reg[2]) : ((PACKET[3:2] == 2'b01) & (vadr_reg[3:2] != 2'b11));
|
default : frueh_ok = 1'b1; // Byte don't case
|
default : frueh_ok = 1'b1; // Byte don't case
|
endcase
|
endcase
|
|
|
assign all_ok = SIZE[1] ? (PACKET[1:0] == 2'b00) : (PACKET[1:0] != 2'b11); // for DWord : Word
|
assign all_ok = SIZE[1] ? (PACKET[1:0] == 2'b00) : (PACKET[1:0] != 2'b11); // for DWord : Word
|
|
|
always @(SIZE or READ_OUT or frueh_ok or PACKET or all_ok or io_acc or acc_ok or qwa_flag or io_rdy or ca_hit)
|
always @(SIZE or READ_OUT or frueh_ok or PACKET or all_ok or io_acc or acc_ok or qwa_flag or io_rdy or ca_hit)
|
casex ({SIZE,READ_OUT,frueh_ok,PACKET[3],io_acc,all_ok})
|
casex ({SIZE,READ_OUT,frueh_ok,PACKET[3],io_acc,all_ok})
|
7'b00_xxxx_x : acc_step = acc_ok; // Byte, all ok
|
7'b00_xxxx_x : acc_step = acc_ok; // Byte, all ok
|
//
|
//
|
7'b01_xxxx_1 : acc_step = acc_ok; // Word : aligned access , only 1 packet
|
7'b01_xxxx_1 : acc_step = acc_ok; // Word : aligned access , only 1 packet
|
7'b01_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
|
7'b01_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
|
7'b01_001x_0 : acc_step = acc_ok; // WRITE Adr. ist not perfect and waits for last packet
|
7'b01_001x_0 : acc_step = acc_ok; // WRITE Adr. ist not perfect and waits for last packet
|
7'b01_01xx_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet
|
7'b01_01xx_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet
|
//
|
//
|
7'b10_xxxx_1 : acc_step = acc_ok; // DWord : aligned access , only 1 packet
|
7'b10_xxxx_1 : acc_step = acc_ok; // DWord : aligned access , only 1 packet
|
7'b10_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
|
7'b10_1x1x_0 : acc_step = acc_ok; // READ must wait for all data
|
7'b10_001x_0 : acc_step = acc_ok; // WRITE Adr. ist not perfect and waits for last packet
|
7'b10_001x_0 : acc_step = acc_ok; // WRITE Adr. ist not perfect and waits for last packet
|
7'b10_01xx_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet
|
7'b10_01xx_0 : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet
|
// fast QWord READ : there would be a 2. acc_step if not ~PACK...
|
// fast QWord READ : there would be a 2. acc_step if not ~PACK...
|
7'b11_1xxx_x : acc_step = acc_ok & ( (qwa_flag & ~io_rdy & ca_hit) ? ~PACKET[3] : PACKET[3] );
|
7'b11_1xxx_x : acc_step = acc_ok & ( (qwa_flag & ~io_rdy & ca_hit) ? ~PACKET[3] : PACKET[3] );
|
7'b11_0x1x_x : acc_step = acc_ok;
|
7'b11_0x1x_x : acc_step = acc_ok;
|
7'b11_0100_x : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet if not io_acc
|
7'b11_0100_x : acc_step = acc_ok; // WRITE Adr. perfect - acc_step after 1. packet if not io_acc
|
default : acc_step = 1'b0;
|
default : acc_step = 1'b0;
|
endcase
|
endcase
|
|
|
// There is a 2. acc_step if packet (10) - this must be suppressed
|
// There is a 2. acc_step if packet (10) - this must be suppressed
|
always @(posedge BCLK or negedge BRESET)
|
always @(posedge BCLK or negedge BRESET)
|
if (!BRESET) no_done <= 1'b0;
|
if (!BRESET) no_done <= 1'b0;
|
else no_done <= (~acc_ende & acc_step) | (no_done & ~(acc_run & acc_ende));
|
else no_done <= (~acc_ende & acc_step) | (no_done & ~(acc_run & acc_ende));
|
|
|
// The final DONE Multiplexer
|
// The final DONE Multiplexer
|
assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;
|
assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;
|
|
|
|
// Bugfix of 7.October 2015
|
|
always @(posedge BCLK) QWATWO <= acc_run & acc_ok & qwa_flag & ~io_rdy & ca_hit & ~PACKET[3] & (SIZE == 2'b11) & READ_OUT & ~no_done;
|
|
|
always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok) | reg_out_i);
|
always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok) | reg_out_i);
|
|
|
always @(posedge BCLK) io_rdy <= IO_READY & (WRITE_OUT | READ_OUT);
|
always @(posedge BCLK) io_rdy <= IO_READY & (WRITE_OUT | READ_OUT);
|
|
|
always @(posedge BCLK) next_reg <= (acc_step & ~qwa_flag) & (SIZE == 2'b11);
|
always @(posedge BCLK) next_reg <= (acc_step & ~qwa_flag) & (SIZE == 2'b11);
|
assign REG_OUT = reg_out_i | next_reg;
|
assign REG_OUT = reg_out_i | next_reg;
|
|
|
endmodule
|
endmodule
|
|
|
