// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: DATENPFAD.v
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// Filename: DATENPFAD.v
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// Version: 3.0 Cache Interface reworked
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// Project: M32632
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// History: 2.1 bug fix of 26 November 2016
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// Version: 3.1 bug fix of 25 February 2019
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// History: 3.0 Cache Interface reworked
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// 2.1 bug fix of 26 November 2016
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// 1.1 bug fix of 7 October 2015
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// 1.1 bug fix of 7 October 2015
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// 1.0 first release of 30 Mai 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 2 December 2018
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// Author: Udo Moeller
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// Date: 8 July 2017
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//
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//
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// Copyright (C) 2018 Udo Moeller
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// Copyright (C) 2019 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// DATENPFAD the data path of M32632
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// DATENPFAD the data path of M32632
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX,
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module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX,
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IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE,
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IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE,
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WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, CTRL_QW, PTB_SEL, PTB_WR, ACB_ZERO,
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WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, CTRL_QW, PTB_SEL, PTB_WR, ACB_ZERO,
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ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG,
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ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, IVAR_MUX, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG,
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DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT);
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DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT);
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input BCLK;
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input BCLK;
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input BRESET;
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input BRESET;
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input WREN; // write enable of the register file
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input WREN; // write enable of the register file
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input IO_READY;
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input IO_READY;
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input LD_DIN;
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input LD_DIN;
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input LD_IMME;
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input LD_IMME;
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input WR_REG; // write signal for the DP_FPU
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input WR_REG; // write signal for the DP_FPU
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input IC_USER;
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input IC_USER;
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input RWVFLAG;
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input RWVFLAG;
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input [14:0] ACC_FELD;
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input [14:0] ACC_FELD;
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input [5:0] ACC_STAT;
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input [5:0] ACC_STAT;
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input [31:0] DIN;
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input [31:0] DIN;
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input [31:0] DISP;
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input [31:0] DISP;
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input [2:0] IC_TEX;
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input [2:0] IC_TEX;
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input [31:0] IMME_Q;
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input [31:0] IMME_Q;
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input [6:0] INFO_AU;
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input [6:0] INFO_AU;
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input [1:0] LD_OUT;
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input [1:0] LD_OUT;
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input [12:0] DETOIP;
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input [12:0] DETOIP;
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input [1:0] MMU_UPDATE;
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input [1:0] MMU_UPDATE;
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input [10:0] OPER;
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input [10:0] OPER;
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input [31:0] PC_ARCHI;
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input [31:0] PC_ARCHI;
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input [31:0] PC_ICACHE;
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input [31:0] PC_ICACHE;
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input [7:0] RDAA;
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input [7:0] RDAA;
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input [7:0] RDAB;
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input [7:0] RDAB;
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input [1:0] START;
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input [1:0] START;
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input [1:0] WMASKE;
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input [1:0] WMASKE;
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input [5:0] WRADR;
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input [5:0] WRADR;
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input DBG_HIT;
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input DBG_HIT;
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input COP_DONE;
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input COP_DONE;
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input [23:0] COP_OP;
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input [23:0] COP_OP;
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input [63:0] COP_IN;
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input [63:0] COP_IN;
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output DONE;
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output DONE;
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output Y_INIT;
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output Y_INIT;
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output WRITE_OUT;
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output WRITE_OUT;
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output READ_OUT;
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output READ_OUT;
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output ZTEST;
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output ZTEST;
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output RMW;
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output RMW;
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output QWATWO;
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output QWATWO;
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output ACC_DONE;
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output ACC_DONE;
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output [1:0] CTRL_QW;
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output [1:0] CTRL_QW;
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output PTB_SEL;
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output PTB_SEL;
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output PTB_WR;
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output PTB_WR;
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output reg ACB_ZERO;
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output reg ACB_ZERO;
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output ABORT;
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output ABORT;
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output SAVE_PC;
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output SAVE_PC;
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output [12:0] CFG;
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output [12:0] CFG;
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output [3:0] CINV;
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output [3:0] CINV;
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output [63:0] DP_Q;
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output [63:0] DP_Q;
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output [1:0] IVAR;
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output [1:0] IVAR;
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output IVAR_MUX;
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output [3:0] MCR;
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output [3:0] MCR;
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output [3:0] PACKET;
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output [3:0] PACKET;
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output [31:0] PC_NEW;
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output [31:0] PC_NEW;
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output [11:0] PSR;
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output [11:0] PSR;
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output [1:0] SIZE;
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output [1:0] SIZE;
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output [4:0] STRING;
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output [4:0] STRING;
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output [5:0] TRAPS;
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output [5:0] TRAPS;
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output [31:0] VADR;
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output [31:0] VADR;
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output [40:2] DBG_IN;
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output [40:2] DBG_IN;
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output COP_GO;
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output COP_GO;
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output [127:0] COP_OUT;
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output [127:0] COP_OUT;
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reg [31:0] high_dq;
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reg [31:0] high_dq;
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reg [31:0] IMMREG,MEMREG;
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reg [31:0] IMMREG,MEMREG;
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reg [31:0] BYDIN; // the bypass register
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reg [31:0] BYDIN; // the bypass register
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reg LDIMR;
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reg LDIMR;
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wire [2:0] BITSEL;
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wire [2:0] BITSEL;
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wire [1:0] BWD;
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wire [1:0] BWD;
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wire CLR_LSB;
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wire CLR_LSB;
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wire [31:0] ERGEBNIS; // the result bus
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wire [31:0] ERGEBNIS; // the result bus
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wire FL;
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wire FL;
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wire [31:0] FSR;
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wire [31:0] FSR;
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wire [32:0] MRESULT;
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wire [32:0] MRESULT;
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wire [7:0] OPCODE;
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wire [7:0] OPCODE;
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wire SELI_A;
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wire SELI_A;
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wire SELI_B;
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wire SELI_B;
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wire [2:0] SP_CMP;
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wire [2:0] SP_CMP;
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wire [31:0] SRC1; // the bus for the Source 1 operand
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wire [31:0] SRC1; // the bus for the Source 1 operand
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wire [31:0] SRC2; // the bus for the Source 2 operand
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wire [31:0] SRC2; // the bus for the Source 2 operand
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wire [31:0] OUT_I;
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wire [31:0] OUT_I;
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wire [4:0] TT_DP;
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wire [4:0] TT_DP;
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wire TWREN; // active if FPU Trap occurs
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wire TWREN; // active if FPU Trap occurs
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wire UP_DP;
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wire UP_DP;
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wire WRADR_0;
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wire WRADR_0;
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wire WREN_L,WREN_LX;
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wire WREN_L,WREN_LX;
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wire LD_FSR;
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wire LD_FSR;
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wire UP_SP;
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wire UP_SP;
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wire [4:0] TT_SP;
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wire [4:0] TT_SP;
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wire [31:0] addr_i;
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wire [31:0] addr_i;
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wire [2:0] DP_CMP;
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wire [2:0] DP_CMP;
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wire [31:0] DP_OUT;
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wire [31:0] DP_OUT;
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wire [31:0] SFP_DAT;
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wire [31:0] SFP_DAT;
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wire [6:0] BMCODE;
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wire [6:0] BMCODE;
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wire [31:0] OUT_A,OUT_B;
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wire [31:0] OUT_A,OUT_B;
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wire SP_MUX;
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wire SP_MUX;
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wire [31:0] I_OUT;
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wire [31:0] I_OUT;
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wire [31:0] FP_OUT;
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wire [31:0] FP_OUT;
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wire DOWR;
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wire DOWR;
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wire [31:0] DEST1,DEST2;
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wire ENWR;
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wire ENWR;
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wire [3:0] OVF_BCD;
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wire [3:0] OVF_BCD;
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wire [3:0] DSR;
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wire [3:0] DSR;
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wire acb_zero_i;
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wire acb_zero_i;
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wire [31:0] BMASKE;
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wire [31:0] BMASKE;
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assign FL = OPER[10];
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assign FL = OPER[10];
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assign BWD = OPER[9:8];
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assign BWD = OPER[9:8];
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assign OPCODE = OPER[7:0];
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assign OPCODE = OPER[7:0];
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assign ERGEBNIS = SP_MUX ? FP_OUT : I_OUT;
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assign ERGEBNIS = SP_MUX ? FP_OUT : I_OUT;
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assign WRADR_0 = WRADR[0] ^ CLR_LSB;
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assign WRADR_0 = WRADR[0] ^ CLR_LSB;
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assign ENWR = WREN_L | WREN;
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assign ENWR = WREN_L | WREN;
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assign DOWR = ENWR & TWREN;
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assign DOWR = ENWR & TWREN;
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assign WREN_L = WREN_LX & ~TRAPS[0];
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assign WREN_L = WREN_LX & ~TRAPS[0];
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assign DP_Q[63:32] = high_dq;
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assign DP_Q[63:32] = high_dq;
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assign PC_NEW = SRC1;
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assign PC_NEW = SRC1;
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always @(posedge BCLK) if (LD_OUT[1] || WREN) ACB_ZERO <= acb_zero_i;
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always @(posedge BCLK) if (LD_OUT[1] || WREN) ACB_ZERO <= acb_zero_i;
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always @(posedge BCLK) if (LD_OUT[1]) high_dq <= ERGEBNIS;
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always @(posedge BCLK) if (LD_OUT[1]) high_dq <= ERGEBNIS;
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (LD_DIN)
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if (LD_DIN)
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begin
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begin
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IMMREG <= IMME_Q;
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IMMREG <= IMME_Q;
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MEMREG <= DIN;
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MEMREG <= DIN;
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LDIMR <= LD_IMME;
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LDIMR <= LD_IMME;
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end
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end
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assign OUT_I = LDIMR ? IMMREG : MEMREG; // old solution had the multiplexor before the register
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assign OUT_I = LDIMR ? IMMREG : MEMREG; // old solution had the multiplexor before the register
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always @(posedge BCLK) if (RDAA[7]) BYDIN <= ERGEBNIS;
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always @(posedge BCLK) if (RDAA[7]) BYDIN <= ERGEBNIS;
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// Register Set 1 => SRC1
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// Register Set 1 => SRC1
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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REGISTER REG_SET_A(
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REGISTER REG_SET_A(
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.BCLK(BCLK),
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.BCLK(BCLK),
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.ENWR(ENWR),
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.ENWR(ENWR),
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.DOWR(DOWR),
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.DOWR(DOWR),
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.DIN(ERGEBNIS),
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.DIN(ERGEBNIS),
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.BYDIN(BYDIN),
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.BYDIN(BYDIN),
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.RADR(RDAA),
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.RADR(RDAA),
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.WADR({WRADR[5:1],WRADR_0}),
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.WADR({WRADR[5:1],WRADR_0}),
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.WMASKE(WMASKE),
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.WMASKE(WMASKE),
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.SELI(SELI_A),
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.SELI(SELI_A),
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.DOUT(OUT_A));
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.DOUT(OUT_A));
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assign SRC1 = SELI_A ? OUT_I : OUT_A;
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assign SRC1 = SELI_A ? OUT_I : OUT_A;
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// Register Set 2 => SRC2
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// Register Set 2 => SRC2
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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REGISTER REG_SET_B(
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REGISTER REG_SET_B(
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.BCLK(BCLK),
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.BCLK(BCLK),
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.ENWR(ENWR),
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.ENWR(ENWR),
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.DOWR(DOWR),
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.DOWR(DOWR),
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.DIN(ERGEBNIS),
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.DIN(ERGEBNIS),
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.BYDIN(BYDIN),
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.BYDIN(BYDIN),
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.RADR(RDAB),
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.RADR(RDAB),
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.WADR({WRADR[5:1],WRADR_0}),
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.WADR({WRADR[5:1],WRADR_0}),
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.WMASKE(WMASKE),
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.WMASKE(WMASKE),
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.SELI(SELI_B),
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.SELI(SELI_B),
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.DOUT(OUT_B));
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.DOUT(OUT_B));
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assign SRC2 = SELI_B ? OUT_I : OUT_B;
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assign SRC2 = SELI_B ? OUT_I : OUT_B;
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MULFILTER M_FILTER( // signed multiplier 32 * 32 bits = 64 bits
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MULFILTER M_FILTER( // signed multiplier 32 * 32 bits = 64 bits
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.BWD(BWD),
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.BWD(BWD),
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.SRC1(SRC1),
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.SRC1(SRC1),
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.SRC2(SRC2),
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.SRC2(SRC2),
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.MRESULT(MRESULT));
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.MRESULT(MRESULT));
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BITMASK BITM_U(
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BITMASK BITM_U(
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.AA(BMCODE),
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.AA(BMCODE),
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.DOUT(BMASKE));
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.DOUT(BMASKE));
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// The integer data path
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// The integer data path
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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I_PFAD GANZ_U(
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I_PFAD GANZ_U(
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.FL(FL),
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.FL(FL),
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.BRESET(BRESET),
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.BRESET(BRESET),
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.BCLK(BCLK),
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.BCLK(BCLK),
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.WREN(WREN),
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.WREN(WREN),
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.LD_OUT(LD_OUT[1]),
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.LD_OUT(LD_OUT[1]),
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.ADDR(addr_i),
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.ADDR(addr_i),
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.BITSEL(BITSEL),
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.BITSEL(BITSEL),
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.BMASKE(BMASKE),
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.BMASKE(BMASKE),
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.BWD(BWD),
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.BWD(BWD),
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.DP_CMP(DP_CMP),
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.DP_CMP(DP_CMP),
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.DP_OUT(DP_OUT),
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.DP_OUT(DP_OUT),
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.FSR(FSR),
|
.FSR(FSR),
|
.DETOIP(DETOIP[11:0]),
|
.DETOIP(DETOIP[11:0]),
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.MRESULT(MRESULT),
|
.MRESULT(MRESULT),
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.OPCODE(OPCODE),
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.OPCODE(OPCODE),
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.RDAA(RDAA),
|
.RDAA(RDAA),
|
.SFP_DAT(SFP_DAT),
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.SFP_DAT(SFP_DAT),
|
.SP_CMP(SP_CMP),
|
.SP_CMP(SP_CMP),
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.SRC1(SRC1),
|
.SRC1(SRC1),
|
.SRC2(SRC2),
|
.SRC2(SRC2),
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.WRADR(WRADR),
|
.WRADR(WRADR),
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.DSR(DSR),
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.DSR(DSR),
|
.OV_FLAG(TRAPS[2]),
|
.OV_FLAG(TRAPS[2]),
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.ACB_ZERO(acb_zero_i),
|
.ACB_ZERO(acb_zero_i),
|
.BMCODE(BMCODE),
|
.BMCODE(BMCODE),
|
.I_OUT(I_OUT),
|
.I_OUT(I_OUT),
|
.PSR(PSR),
|
.PSR(PSR),
|
.STRING(STRING),
|
.STRING(STRING),
|
.OVF_BCD(OVF_BCD),
|
.OVF_BCD(OVF_BCD),
|
.DISP(DISP[4:0]),
|
.DISP(DISP[4:0]),
|
.RWVFLAG(RWVFLAG));
|
.RWVFLAG(RWVFLAG));
|
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// The address unit
|
// The address unit
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
ADDR_UNIT ADDR_U(
|
ADDR_UNIT ADDR_U(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.IO_READY(IO_READY),
|
.IO_READY(IO_READY),
|
.READ(ACC_FELD[11]),
|
.READ(ACC_FELD[11]),
|
.WRITE(ACC_FELD[10]),
|
.WRITE(ACC_FELD[10]),
|
.CLRMSW(ACC_FELD[2]),
|
.CLRMSW(ACC_FELD[2]),
|
.FULLACC(ACC_FELD[8]),
|
.FULLACC(ACC_FELD[8]),
|
.POST(ACC_FELD[3]),
|
.POST(ACC_FELD[3]),
|
.DISP_OK(INFO_AU[0]),
|
.DISP_OK(INFO_AU[0]),
|
.LDEA(ACC_FELD[9]),
|
.LDEA(ACC_FELD[9]),
|
.NEWACC(ACC_FELD[14]),
|
.NEWACC(ACC_FELD[14]),
|
.FPU_TRAP(TRAPS[0]),
|
.FPU_TRAP(TRAPS[0]),
|
.ADIVAR(INFO_AU[2]),
|
.ADIVAR(INFO_AU[2]),
|
.RWVAL_1(INFO_AU[3]),
|
.RWVAL_1(INFO_AU[3]),
|
.ABO_STAT({INFO_AU[1],IC_USER}),
|
.ABO_STAT({INFO_AU[1],IC_USER}),
|
.ACC_STAT(ACC_STAT),
|
.ACC_STAT(ACC_STAT),
|
.ASIZE(ACC_FELD[13:12]),
|
.ASIZE(ACC_FELD[13:12]),
|
.BWD(BWD),
|
.BWD(BWD),
|
.DISP(DISP),
|
.DISP(DISP),
|
.IC_TEX(IC_TEX),
|
.IC_TEX(IC_TEX),
|
.INDEX(ACC_FELD[7:4]),
|
.INDEX(ACC_FELD[7:4]),
|
.MMU_UPDATE(MMU_UPDATE),
|
.MMU_UPDATE(MMU_UPDATE),
|
.PC_ARCHI(PC_ARCHI),
|
.PC_ARCHI(PC_ARCHI),
|
.PC_ICACHE(PC_ICACHE),
|
.PC_ICACHE(PC_ICACHE),
|
.SRC1(SRC1),
|
.SRC1(SRC1),
|
.SRC2(SRC2),
|
.SRC2(SRC2),
|
.SRC2SEL(ACC_FELD[1:0]),
|
.SRC2SEL(ACC_FELD[1:0]),
|
.CTRL_QW(CTRL_QW),
|
.CTRL_QW(CTRL_QW),
|
.ACC_DONE(ACC_DONE),
|
.ACC_DONE(ACC_DONE),
|
.READ_OUT(READ_OUT),
|
.READ_OUT(READ_OUT),
|
.WRITE_OUT(WRITE_OUT),
|
.WRITE_OUT(WRITE_OUT),
|
.ABORT(ABORT),
|
.ABORT(ABORT),
|
.ADDR(addr_i),
|
.ADDR(addr_i),
|
.BITSEL(BITSEL),
|
.BITSEL(BITSEL),
|
.PACKET(PACKET),
|
.PACKET(PACKET),
|
.SIZE(SIZE),
|
.SIZE(SIZE),
|
.VADR(VADR),
|
.VADR(VADR),
|
.ZTEST(ZTEST),
|
.ZTEST(ZTEST),
|
.RMW(RMW),
|
.RMW(RMW),
|
.QWATWO(QWATWO),
|
.QWATWO(QWATWO),
|
.OP_RMW(INFO_AU[4]),
|
.OP_RMW(INFO_AU[4]),
|
.PHASE_17(INFO_AU[5]),
|
.PHASE_17(INFO_AU[5]),
|
.NO_TRAP(INFO_AU[6]) );
|
.NO_TRAP(INFO_AU[6]) );
|
|
|
CONFIG_REGS CFG_DBG(
|
CONFIG_REGS CFG_DBG(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.WREN(WREN),
|
.WREN(WREN),
|
.LD_OUT(LD_OUT[1]),
|
.LD_OUT(LD_OUT[1]),
|
.OPCODE(OPCODE),
|
.OPCODE(OPCODE),
|
.SRC1(SRC1),
|
.SRC1(SRC1),
|
.WRADR(WRADR),
|
.WRADR(WRADR),
|
.PTB_WR(PTB_WR),
|
.PTB_WR(PTB_WR),
|
.PTB_SEL(PTB_SEL),
|
.PTB_SEL(PTB_SEL),
|
.CFG(CFG),
|
.CFG(CFG),
|
.CINV(CINV),
|
.CINV(CINV),
|
.IVAR(IVAR),
|
.IVAR(IVAR),
|
|
.IVAR_MUX(IVAR_MUX),
|
.Y_INIT(Y_INIT),
|
.Y_INIT(Y_INIT),
|
.MCR(MCR),
|
.MCR(MCR),
|
.DBG_TRAPS(TRAPS[5:3]),
|
.DBG_TRAPS(TRAPS[5:3]),
|
.PC_ARCHI(PC_ARCHI),
|
.PC_ARCHI(PC_ARCHI),
|
.DSR(DSR),
|
.DSR(DSR),
|
.USER(PSR[8]),
|
.USER(PSR[8]),
|
.PCMATCH(DETOIP[12]),
|
.PCMATCH(DETOIP[12]),
|
.DBG_IN(DBG_IN),
|
.DBG_IN(DBG_IN),
|
.DBG_HIT(DBG_HIT),
|
.DBG_HIT(DBG_HIT),
|
.READ(READ_OUT) );
|
.READ(READ_OUT) );
|
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// The long operation unit
|
// The long operation unit
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
DP_FPU DOUBLE_U(
|
DP_FPU DOUBLE_U(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.FL(FL),
|
.FL(FL),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.LD_OUT(LD_OUT),
|
.LD_OUT(LD_OUT),
|
.WR_REG(WR_REG),
|
.WR_REG(WR_REG),
|
.BWD(BWD),
|
.BWD(BWD),
|
.FSR(FSR[8:3]),
|
.FSR(FSR[8:3]),
|
.OPCODE(OPCODE),
|
.OPCODE(OPCODE),
|
.SRC1(SRC1),
|
.SRC1(SRC1),
|
.SRC2(SRC2),
|
.SRC2(SRC2),
|
.START(START),
|
.START(START),
|
.DONE(DONE),
|
.DONE(DONE),
|
.UP_DP(UP_DP),
|
.UP_DP(UP_DP),
|
.WREN_L(WREN_LX),
|
.WREN_L(WREN_LX),
|
.CLR_LSB(CLR_LSB),
|
.CLR_LSB(CLR_LSB),
|
.DVZ_TRAP(TRAPS[1]),
|
.DVZ_TRAP(TRAPS[1]),
|
.DP_CMP(DP_CMP),
|
.DP_CMP(DP_CMP),
|
.DP_OUT(DP_OUT),
|
.DP_OUT(DP_OUT),
|
.DP_Q(DP_Q[31:0]),
|
.DP_Q(DP_Q[31:0]),
|
.TT_DP(TT_DP),
|
.TT_DP(TT_DP),
|
.CY_IN(PSR[0]),
|
.CY_IN(PSR[0]),
|
.OVF_BCD(OVF_BCD),
|
.OVF_BCD(OVF_BCD),
|
.COP_DONE(COP_DONE),
|
.COP_DONE(COP_DONE),
|
.COP_OP(COP_OP),
|
.COP_OP(COP_OP),
|
.COP_IN(COP_IN),
|
.COP_IN(COP_IN),
|
.COP_GO(COP_GO),
|
.COP_GO(COP_GO),
|
.COP_OUT(COP_OUT));
|
.COP_OUT(COP_OUT));
|
|
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// The single precision floating point unit
|
// The single precision floating point unit
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
SP_FPU SINGLE_U(
|
SP_FPU SINGLE_U(
|
.FL(FL),
|
.FL(FL),
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.BWD(BWD),
|
.BWD(BWD),
|
.FSR(FSR[8:3]),
|
.FSR(FSR[8:3]),
|
.OPCODE(OPCODE),
|
.OPCODE(OPCODE),
|
.SRC1(SRC1),
|
.SRC1(SRC1),
|
.SRC2(SRC2),
|
.SRC2(SRC2),
|
.LD_FSR(LD_FSR),
|
.LD_FSR(LD_FSR),
|
.SP_MUX(SP_MUX),
|
.SP_MUX(SP_MUX),
|
.UP_SP(UP_SP),
|
.UP_SP(UP_SP),
|
.FP_OUT(FP_OUT),
|
.FP_OUT(FP_OUT),
|
.I_OUT(SFP_DAT),
|
.I_OUT(SFP_DAT),
|
.SP_CMP(SP_CMP),
|
.SP_CMP(SP_CMP),
|
.TT_SP(TT_SP),
|
.TT_SP(TT_SP),
|
.START(START[1]) ); // Aenderung
|
.START(START[1]) ); // Aenderung
|
|
|
FP_STAT_REG FPS_REG(
|
FP_STAT_REG FPS_REG(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.LFSR(LD_FSR),
|
.LFSR(LD_FSR),
|
.WREN(ENWR),
|
.WREN(ENWR),
|
.WRADR(WRADR[5:4]),
|
.WRADR(WRADR[5:4]),
|
.UP_DP(UP_DP),
|
.UP_DP(UP_DP),
|
.UP_SP(UP_SP), // & LD_OUT[1]), Aenderung
|
.UP_SP(UP_SP), // & LD_OUT[1]), Aenderung
|
.DIN(SRC1[16:0]),
|
.DIN(SRC1[16:0]),
|
.TT_DP(TT_DP),
|
.TT_DP(TT_DP),
|
.TT_SP(TT_SP),
|
.TT_SP(TT_SP),
|
.FPU_TRAP(TRAPS[0]),
|
.FPU_TRAP(TRAPS[0]),
|
.TWREN(TWREN),
|
.TWREN(TWREN),
|
.SAVE_PC(SAVE_PC),
|
.SAVE_PC(SAVE_PC),
|
.FSR(FSR));
|
.FSR(FSR));
|
|
|
endmodule
|
endmodule
|
|
|
