// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: DCACHE.v
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// Filename: DCACHE.v
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// Version: 1.0
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// Version: 1.1 bug fix
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// Date: 30 May 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 7 October 2015
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2015 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// DCACHE the data cache of M32632
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// DCACHE the data cache of M32632
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module DCACHE( BCLK, MCLK, WRCFG, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW,
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module DCACHE( BCLK, MCLK, WRCFG, MDONE, BRESET, PTB_WR, PTB_SEL, IO_READY, REG_OUT, PSR_USER, WRITE, READ, RMW, QWATWO,
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WAMUX, ENWR, IC_PREQ, FILLRAM, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR, MCR_FLAGS,
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WAMUX, ENWR, IC_PREQ, FILLRAM, CFG, CINVAL, DMA_AA, DP_Q, DRAM_Q, IC_VA, ICTODC, IO_Q, IVAR, MCR_FLAGS,
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PACKET, SIZE, VADR, WADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET, HLDA,
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PACKET, SIZE, VADR, WADDR, WCTRL, IO_RD, IO_WR, DRAM_ACC, DRAM_WR, INIT_RUN, PTE_STAT, KDET, HLDA,
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ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
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ACC_STAT, DP_DI, DRAM_A, DRAM_DI, IACC_STAT, IC_SIGS, IO_A, IO_BE, IO_DI, KOLLI_A, MMU_DIN, ZTEST,
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RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
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RWVAL, RWVFLAG, DBG_IN, DBG_HIT, ENDRAM );
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input BCLK;
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input BCLK;
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input MCLK;
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input MCLK;
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input WRCFG;
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input WRCFG;
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input MDONE;
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input MDONE;
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input BRESET;
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input BRESET;
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input PTB_WR;
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input PTB_WR;
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input PTB_SEL;
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input PTB_SEL;
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input IO_READY;
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input IO_READY;
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input REG_OUT;
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input REG_OUT;
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input PSR_USER;
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input PSR_USER;
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input WRITE;
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input WRITE;
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input READ;
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input READ;
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input ZTEST;
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input ZTEST;
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input RMW;
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input RMW;
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input QWATWO;
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input WAMUX;
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input WAMUX;
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input ENWR;
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input ENWR;
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input IC_PREQ;
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input IC_PREQ;
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input FILLRAM;
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input FILLRAM;
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input [1:0] CFG;
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input [1:0] CFG;
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input [1:0] CINVAL;
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input [1:0] CINVAL;
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input [27:4] DMA_AA;
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input [27:4] DMA_AA;
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input [63:0] DP_Q;
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input [63:0] DP_Q;
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input [31:0] DRAM_Q;
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input [31:0] DRAM_Q;
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input [31:12] IC_VA;
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input [31:12] IC_VA;
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input [3:0] ICTODC;
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input [3:0] ICTODC;
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input [31:0] IO_Q;
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input [31:0] IO_Q;
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input [1:0] IVAR;
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input [1:0] IVAR;
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input [3:0] MCR_FLAGS;
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input [3:0] MCR_FLAGS;
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input [3:0] PACKET;
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input [3:0] PACKET;
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input [1:0] SIZE;
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input [1:0] SIZE;
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input [31:0] VADR;
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input [31:0] VADR;
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input [11:2] WADDR;
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input [11:2] WADDR;
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input [2:0] WCTRL;
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input [2:0] WCTRL;
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input [2:0] RWVAL;
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input [2:0] RWVAL;
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input [40:2] DBG_IN;
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input [40:2] DBG_IN;
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input ENDRAM;
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input ENDRAM;
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output IO_RD;
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output IO_RD;
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output IO_WR;
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output IO_WR;
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output DRAM_ACC;
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output DRAM_ACC;
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output DRAM_WR;
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output DRAM_WR;
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output INIT_RUN;
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output INIT_RUN;
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output [1:0] PTE_STAT;
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output [1:0] PTE_STAT;
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output KDET;
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output KDET;
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output HLDA;
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output HLDA;
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output RWVFLAG;
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output RWVFLAG;
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output [5:0] ACC_STAT;
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output [5:0] ACC_STAT;
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output [31:0] DP_DI;
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output [31:0] DP_DI;
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output [3:1] IACC_STAT;
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output [3:1] IACC_STAT;
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output [1:0] IC_SIGS;
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output [1:0] IC_SIGS;
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output [27:4] KOLLI_A;
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output [27:4] KOLLI_A;
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output [23:0] MMU_DIN;
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output [23:0] MMU_DIN;
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output reg [27:0] DRAM_A;
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output reg [27:0] DRAM_A;
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output reg [35:0] DRAM_DI;
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output reg [35:0] DRAM_DI;
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output reg [31:0] IO_A;
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output reg [31:0] IO_A;
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output reg [3:0] IO_BE;
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output reg [3:0] IO_BE;
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output reg [31:0] IO_DI;
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output reg [31:0] IO_DI;
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output DBG_HIT;
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output DBG_HIT;
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reg [31:0] DFFE_IOR;
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reg [31:0] DFFE_IOR;
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reg [31:0] CAPDAT;
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reg [31:0] CAPDAT;
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reg [31:0] VADR_R;
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reg [31:0] VADR_R;
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reg AUX_ALT;
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reg AUX_ALT;
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reg DFF_QWEXT;
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reg DFF_QWEXT;
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wire [27:4] ADDR;
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wire [27:4] ADDR;
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wire ADR_EQU;
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wire ADR_EQU;
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wire AUX_DAT;
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wire AUX_DAT;
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wire CA_HIT;
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wire CA_HIT;
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wire CA_SET;
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wire CA_SET;
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wire CUPDATE;
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wire CUPDATE;
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wire DMA_MUX;
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wire DMA_MUX;
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wire [3:0] ENBYTE;
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wire [3:0] ENBYTE;
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wire HIT_ALL;
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wire HIT_ALL;
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wire INIT_CA_RUN;
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wire INIT_CA_RUN;
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wire IO_ACC;
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wire IO_ACC;
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wire IO_SPACE;
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wire IO_SPACE;
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wire KOMUX;
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wire KOMUX;
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wire MMU_HIT;
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wire MMU_HIT;
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wire NEW_PTB;
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wire NEW_PTB;
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wire PTB_ONE;
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wire PTB_ONE;
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wire [27:0] PTE_ADR;
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wire [27:0] PTE_ADR;
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wire [31:12] RADR;
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wire [31:12] RADR;
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wire [11:4] TAGA;
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wire [11:4] TAGA;
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wire [23:0] UPDATE_C;
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wire [23:0] UPDATE_C;
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wire [31:0] UPDATE_M;
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wire [31:0] UPDATE_M;
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wire USE_CA;
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wire USE_CA;
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wire USER;
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wire USER;
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wire WB_ACC;
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wire WB_ACC;
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wire WEMV;
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wire WEMV;
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wire WR_MRAM;
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wire WR_MRAM;
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wire [31:0] WRDATA;
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wire [31:0] WRDATA;
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wire VIRT_A;
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wire VIRT_A;
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wire PTE_MUX;
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wire PTE_MUX;
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wire WE_CV;
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wire WE_CV;
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wire [23:0] DAT_CV;
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wire [23:0] DAT_CV;
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wire [4:0] WADR_CV;
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wire [4:0] WADR_CV;
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wire WRSET0;
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wire WRSET0;
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wire [3:0] BE_SET;
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wire [3:0] BE_SET;
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wire [31:0] DAT_SET;
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wire [31:0] DAT_SET;
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wire [9:0] A_SET;
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wire [9:0] A_SET;
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wire WRSET1;
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wire WRSET1;
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wire SEL_PTB1;
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wire SEL_PTB1;
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wire CI;
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wire CI;
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wire [27:0] ADR_MX;
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wire [27:0] ADR_MX;
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wire LD_DRAM_A;
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wire LD_DRAM_A;
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wire VIRTUELL;
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wire VIRTUELL;
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wire NEW_PTB_RUN;
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wire NEW_PTB_RUN;
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wire KILL;
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wire KILL;
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wire LAST_MUX;
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wire LAST_MUX;
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wire [31:0] SET_DAT;
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wire [31:0] SET_DAT;
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wire [31:0] ALT_DAT;
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wire [31:0] ALT_DAT;
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wire [31:0] DAT_MV;
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wire [31:0] DAT_MV;
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wire [3:0] RADR_MV;
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wire [3:0] RADR_MV;
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wire [3:0] WADR_MV;
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wire [3:0] WADR_MV;
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wire [31:0] LAST_DAT;
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wire [31:0] LAST_DAT;
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wire WRCRAM0;
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wire WRCRAM0;
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wire WRCRAM1;
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wire WRCRAM1;
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wire PROT_ERROR;
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wire PROT_ERROR;
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wire AUX_QW;
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wire AUX_QW;
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wire PD_MUX;
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wire PD_MUX;
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wire [19:0] PTE_DAT;
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wire [19:0] PTE_DAT;
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wire PKEEP;
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wire PKEEP;
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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reg [7:0] DATA0_D [0:1023]; // Data Set 0 : 4 kBytes
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reg [7:0] DATA0_D [0:1023]; // Data Set 0 : 4 kBytes
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reg [7:0] DATA0_C [0:1023];
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reg [7:0] DATA0_C [0:1023];
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reg [7:0] DATA0_B [0:1023];
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reg [7:0] DATA0_B [0:1023];
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reg [7:0] DATA0_A [0:1023];
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reg [7:0] DATA0_A [0:1023];
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reg [31:0] SET_DAT0;
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reg [31:0] SET_DAT0;
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reg [7:0] DATA1_D [0:1023]; // Data Set 1 : 4 kBytes
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reg [7:0] DATA1_D [0:1023]; // Data Set 1 : 4 kBytes
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reg [7:0] DATA1_C [0:1023];
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reg [7:0] DATA1_C [0:1023];
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reg [7:0] DATA1_B [0:1023];
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reg [7:0] DATA1_B [0:1023];
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reg [7:0] DATA1_A [0:1023];
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reg [7:0] DATA1_A [0:1023];
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reg [31:0] SET_DAT1;
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reg [31:0] SET_DAT1;
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reg [15:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 16 bits
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reg [15:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 16 bits
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reg [15:0] TAG0;
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reg [15:0] TAG0;
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reg [15:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 16 bits
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reg [15:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 16 bits
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reg [15:0] TAG1;
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reg [15:0] TAG1;
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reg [23:0] CA_VALID [0:31]; // Valid bits for Data Set 0 and 1 : 32 entries of 24 bits
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reg [23:0] CA_VALID [0:31]; // Valid bits for Data Set 0 and 1 : 32 entries of 24 bits
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reg [23:0] CVALID;
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reg [23:0] CVALID;
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reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
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reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
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reg [35:0] MMU_Q;
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reg [35:0] MMU_Q;
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reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
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reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
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reg [31:0] MVALID;
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reg [31:0] MVALID;
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assign ADR_EQU = ({RADR[27:12],VADR_R[11:4]} == DRAM_A[27:4]); // Limited to 256 MB
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assign ADR_EQU = ({RADR[27:12],VADR_R[11:4]} == DRAM_A[27:4]); // Limited to 256 MB
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assign ALT_DAT = AUX_ALT ? DFFE_IOR : CAPDAT ;
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assign ALT_DAT = AUX_ALT ? DFFE_IOR : CAPDAT ;
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assign RADR = VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;
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assign RADR = VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;
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assign ADR_MX = PTE_MUX ? PTE_ADR : {RADR[27:12],VADR_R[11:2],USE_CA,CA_SET} ;
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assign ADR_MX = PTE_MUX ? PTE_ADR : {RADR[27:12],VADR_R[11:2],USE_CA,CA_SET} ;
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assign KOLLI_A = DMA_MUX ? DMA_AA : DRAM_A[27:4] ;
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assign KOLLI_A = DMA_MUX ? DMA_AA : DRAM_A[27:4] ;
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assign SET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;
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assign SET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;
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assign VIRT_A = ~CINVAL[0] & VIRTUELL;
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assign VIRT_A = ~CINVAL[0] & VIRTUELL;
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assign USER = ~MCR_FLAGS[3] & PSR_USER;
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assign USER = ~MCR_FLAGS[3] & PSR_USER;
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assign DAT_SET = WRITE ? WRDATA : DRAM_Q ;
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assign DAT_SET = WRITE ? WRDATA : DRAM_Q ;
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assign BE_SET = ENBYTE | {~WRITE,~WRITE,~WRITE,~WRITE};
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assign BE_SET = ENBYTE | {~WRITE,~WRITE,~WRITE,~WRITE};
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assign ADDR = KOMUX ? KOLLI_A : {RADR[27:12],VADR_R[11:4]} ;
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assign ADDR = KDET ? KOLLI_A : {RADR[27:12],VADR_R[11:4]} ;
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assign A_SET = WAMUX ? WADDR : VADR_R[11:2] ;
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assign A_SET = WAMUX ? WADDR : VADR_R[11:2] ;
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assign TAGA = KOMUX ? KOLLI_A[11:4] : VADR[11:4] ;
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assign TAGA = KOMUX ? KOLLI_A[11:4] : VADR[11:4] ;
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assign INIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;
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assign INIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;
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assign LAST_MUX = AUX_ALT | AUX_DAT | AUX_QW;
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assign LAST_MUX = AUX_ALT | AUX_DAT | AUX_QW;
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assign LAST_DAT = LAST_MUX ? ALT_DAT : SET_DAT ;
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assign LAST_DAT = LAST_MUX ? ALT_DAT : SET_DAT ;
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assign LD_DRAM_A = ~(DRAM_ACC | PKEEP);
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assign LD_DRAM_A = ~(DRAM_ACC | PKEEP);
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assign ACC_STAT[4] = IO_ACC;
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assign ACC_STAT[4] = IO_ACC;
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assign ACC_STAT[5] = CA_HIT;
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assign ACC_STAT[5] = CA_HIT;
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (IO_ACC)
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if (IO_ACC)
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begin
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begin
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IO_BE <= ENBYTE;
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IO_BE <= ENBYTE;
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IO_DI <= WRDATA;
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IO_DI <= WRDATA;
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IO_A <= {RADR[31:12],VADR_R[11:0]};
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IO_A <= {RADR[31:12],VADR_R[11:0]};
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end
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end
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always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[27:0] <= ADR_MX[27:0];
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always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[27:0] <= ADR_MX[27:0];
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always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
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always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
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always @(posedge BCLK)
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always @(posedge BCLK)
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begin
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begin
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DRAM_DI <= {(PD_MUX ? PTE_DAT[19:16] : ENBYTE),WRDATA[31:16],
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DRAM_DI <= {(PD_MUX ? PTE_DAT[19:16] : ENBYTE),WRDATA[31:16],
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(PD_MUX ? PTE_DAT[15:0] : WRDATA[15:0])};
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(PD_MUX ? PTE_DAT[15:0] : WRDATA[15:0])};
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AUX_ALT <= DFF_QWEXT | IO_RD;
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AUX_ALT <= DFF_QWEXT | IO_RD;
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DFF_QWEXT <= IO_RD & SIZE[0] & SIZE[1];
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DFF_QWEXT <= IO_RD & SIZE[0] & SIZE[1];
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VADR_R <= VADR;
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VADR_R <= VADR;
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end
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end
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always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;
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always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;
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// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
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// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
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always @(posedge BCLK) CVALID <= CA_VALID[TAGA[11:7]];
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always @(posedge BCLK) CVALID <= CA_VALID[TAGA[11:7]];
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always @(negedge BCLK) if (WE_CV) CA_VALID[WADR_CV] <= DAT_CV;
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always @(negedge BCLK) if (WE_CV) CA_VALID[WADR_CV] <= DAT_CV;
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// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
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// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
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always @(posedge BCLK) TAG0 <= TAGSET_0[TAGA];
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always @(posedge BCLK) TAG0 <= TAGSET_0[TAGA];
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always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= RADR[27:12];
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always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= RADR[27:12];
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// +++++++++++++++++++++++++ Tag Set 1 +++++++++++++++++++++
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// +++++++++++++++++++++++++ Tag Set 1 +++++++++++++++++++++
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always @(posedge BCLK) TAG1 <= TAGSET_1[TAGA];
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always @(posedge BCLK) TAG1 <= TAGSET_1[TAGA];
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always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= RADR[27:12];
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always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= RADR[27:12];
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// +++++++++++++++++++++++++ Data Set 0 ++++++++++++++++++++
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// +++++++++++++++++++++++++ Data Set 0 ++++++++++++++++++++
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always @(posedge BCLK)
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always @(posedge BCLK)
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begin
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begin
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SET_DAT0[31:24] <= DATA0_D[VADR[11:2]];
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SET_DAT0[31:24] <= DATA0_D[VADR[11:2]];
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SET_DAT0[23:16] <= DATA0_C[VADR[11:2]];
|
SET_DAT0[23:16] <= DATA0_C[VADR[11:2]];
|
SET_DAT0[15:8] <= DATA0_B[VADR[11:2]];
|
SET_DAT0[15:8] <= DATA0_B[VADR[11:2]];
|
SET_DAT0[7:0] <= DATA0_A[VADR[11:2]];
|
SET_DAT0[7:0] <= DATA0_A[VADR[11:2]];
|
end
|
end
|
|
|
always @(posedge MCLK)
|
always @(posedge MCLK)
|
if (WRSET0)
|
if (WRSET0)
|
begin
|
begin
|
if (BE_SET[3]) DATA0_D[A_SET] <= DAT_SET[31:24];
|
if (BE_SET[3]) DATA0_D[A_SET] <= DAT_SET[31:24];
|
if (BE_SET[2]) DATA0_C[A_SET] <= DAT_SET[23:16];
|
if (BE_SET[2]) DATA0_C[A_SET] <= DAT_SET[23:16];
|
if (BE_SET[1]) DATA0_B[A_SET] <= DAT_SET[15:8];
|
if (BE_SET[1]) DATA0_B[A_SET] <= DAT_SET[15:8];
|
if (BE_SET[0]) DATA0_A[A_SET] <= DAT_SET[7:0];
|
if (BE_SET[0]) DATA0_A[A_SET] <= DAT_SET[7:0];
|
end
|
end
|
|
|
// +++++++++++++++++++++++++ Data Set 1 ++++++++++++++++++++
|
// +++++++++++++++++++++++++ Data Set 1 ++++++++++++++++++++
|
|
|
always @(posedge BCLK)
|
always @(posedge BCLK)
|
begin
|
begin
|
SET_DAT1[31:24] <= DATA1_D[VADR[11:2]];
|
SET_DAT1[31:24] <= DATA1_D[VADR[11:2]];
|
SET_DAT1[23:16] <= DATA1_C[VADR[11:2]];
|
SET_DAT1[23:16] <= DATA1_C[VADR[11:2]];
|
SET_DAT1[15:8] <= DATA1_B[VADR[11:2]];
|
SET_DAT1[15:8] <= DATA1_B[VADR[11:2]];
|
SET_DAT1[7:0] <= DATA1_A[VADR[11:2]];
|
SET_DAT1[7:0] <= DATA1_A[VADR[11:2]];
|
end
|
end
|
|
|
always @(posedge MCLK)
|
always @(posedge MCLK)
|
if (WRSET1)
|
if (WRSET1)
|
begin
|
begin
|
if (BE_SET[3]) DATA1_D[A_SET] <= DAT_SET[31:24];
|
if (BE_SET[3]) DATA1_D[A_SET] <= DAT_SET[31:24];
|
if (BE_SET[2]) DATA1_C[A_SET] <= DAT_SET[23:16];
|
if (BE_SET[2]) DATA1_C[A_SET] <= DAT_SET[23:16];
|
if (BE_SET[1]) DATA1_B[A_SET] <= DAT_SET[15:8];
|
if (BE_SET[1]) DATA1_B[A_SET] <= DAT_SET[15:8];
|
if (BE_SET[0]) DATA1_A[A_SET] <= DAT_SET[7:0];
|
if (BE_SET[0]) DATA1_A[A_SET] <= DAT_SET[7:0];
|
end
|
end
|
|
|
DCACHE_SM DC_SM(
|
DCACHE_SM DC_SM(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.VIRTUELL(VIRTUELL),
|
.VIRTUELL(VIRTUELL),
|
.IO_SPACE(IO_SPACE),
|
.IO_SPACE(IO_SPACE),
|
.MDONE(MDONE),
|
.MDONE(MDONE),
|
.MMU_HIT(MMU_HIT),
|
.MMU_HIT(MMU_HIT),
|
.CA_HIT(CA_HIT),
|
.CA_HIT(CA_HIT),
|
.READ(READ),
|
.READ(READ),
|
.WRITE(WRITE),
|
.WRITE(WRITE),
|
.ZTEST(ZTEST),
|
.ZTEST(ZTEST),
|
.RMW(RMW),
|
.RMW(RMW),
|
|
.QWATWO(QWATWO),
|
.USE_CA(USE_CA),
|
.USE_CA(USE_CA),
|
.PTB_WR(PTB_WR),
|
.PTB_WR(PTB_WR),
|
.PTB_SEL(PTB_SEL),
|
.PTB_SEL(PTB_SEL),
|
.SEL_PTB1(SEL_PTB1),
|
.SEL_PTB1(SEL_PTB1),
|
.IO_READY(IO_READY),
|
.IO_READY(IO_READY),
|
.USER(USER),
|
.USER(USER),
|
.PROTECT(ACC_STAT[3]),
|
.PROTECT(ACC_STAT[3]),
|
.PROT_ERROR(PROT_ERROR),
|
.PROT_ERROR(PROT_ERROR),
|
.ENWR(ENWR),
|
.ENWR(ENWR),
|
.WB_ACC(WB_ACC),
|
.WB_ACC(WB_ACC),
|
.ADR_EQU(ADR_EQU),
|
.ADR_EQU(ADR_EQU),
|
.IC_PREQ(IC_PREQ),
|
.IC_PREQ(IC_PREQ),
|
.CAPDAT(CAPDAT[31:0]),
|
.CAPDAT(CAPDAT[31:0]),
|
.CPU_OUT(DP_Q[59:44]),
|
.CPU_OUT(DP_Q[59:44]),
|
.FILLRAM(FILLRAM),
|
.FILLRAM(FILLRAM),
|
.IC_VA(IC_VA),
|
.IC_VA(IC_VA),
|
.ICTODC(ICTODC),
|
.ICTODC(ICTODC),
|
.VADR_R(VADR_R[31:12]),
|
.VADR_R(VADR_R[31:12]),
|
.NEW_PTB(NEW_PTB),
|
.NEW_PTB(NEW_PTB),
|
.PTB_ONE(PTB_ONE),
|
.PTB_ONE(PTB_ONE),
|
.DRAM_ACC(DRAM_ACC),
|
.DRAM_ACC(DRAM_ACC),
|
.DRAM_WR(DRAM_WR),
|
.DRAM_WR(DRAM_WR),
|
.IO_ACC(IO_ACC),
|
.IO_ACC(IO_ACC),
|
.IO_RD(IO_RD),
|
.IO_RD(IO_RD),
|
.IO_WR(IO_WR),
|
.IO_WR(IO_WR),
|
.PTE_STAT(PTE_STAT),
|
.PTE_STAT(PTE_STAT),
|
.ABORT(ACC_STAT[1]),
|
.ABORT(ACC_STAT[1]),
|
.WR_MRAM(WR_MRAM),
|
.WR_MRAM(WR_MRAM),
|
.CUPDATE(CUPDATE),
|
.CUPDATE(CUPDATE),
|
.AUX_DAT(AUX_DAT),
|
.AUX_DAT(AUX_DAT),
|
.PTE_MUX(PTE_MUX),
|
.PTE_MUX(PTE_MUX),
|
.ACC_OK(ACC_STAT[0]),
|
.ACC_OK(ACC_STAT[0]),
|
.ABO_LEVEL1(ACC_STAT[2]),
|
.ABO_LEVEL1(ACC_STAT[2]),
|
.IACC_STAT(IACC_STAT),
|
.IACC_STAT(IACC_STAT),
|
.KOMUX(KOMUX),
|
.KOMUX(KOMUX),
|
.KDET(KDET),
|
.KDET(KDET),
|
.HIT_ALL(HIT_ALL),
|
.HIT_ALL(HIT_ALL),
|
.DMA_MUX(DMA_MUX),
|
.DMA_MUX(DMA_MUX),
|
.HLDA(HLDA),
|
.HLDA(HLDA),
|
.RWVAL(RWVAL[1:0]),
|
.RWVAL(RWVAL[1:0]),
|
.RWVFLAG(RWVFLAG),
|
.RWVFLAG(RWVFLAG),
|
.IC_SIGS(IC_SIGS),
|
.IC_SIGS(IC_SIGS),
|
.MMU_DIN(MMU_DIN),
|
.MMU_DIN(MMU_DIN),
|
.PD_MUX(PD_MUX),
|
.PD_MUX(PD_MUX),
|
.PKEEP(PKEEP),
|
.PKEEP(PKEEP),
|
.PTE_ADR(PTE_ADR),
|
.PTE_ADR(PTE_ADR),
|
.PTE_DAT(PTE_DAT));
|
.PTE_DAT(PTE_DAT));
|
|
|
CA_MATCH DCA_COMPARE(
|
CA_MATCH DCA_COMPARE(
|
.INVAL_L(CINVAL[0]),
|
.INVAL_L(CINVAL[0]),
|
.CI(CI),
|
.CI(CI),
|
.MMU_HIT(MMU_HIT),
|
.MMU_HIT(MMU_HIT),
|
.WRITE(WRITE),
|
.WRITE(WRITE),
|
.KDET(KDET),
|
.KDET(KDET),
|
.ADDR(ADDR),
|
.ADDR(ADDR),
|
.CFG(CFG),
|
.CFG(CFG),
|
.ENDRAM(ENDRAM),
|
.ENDRAM(ENDRAM),
|
.CVALID(CVALID),
|
.CVALID(CVALID),
|
.TAG0(TAG0),
|
.TAG0(TAG0),
|
.TAG1(TAG1),
|
.TAG1(TAG1),
|
.CA_HIT(CA_HIT),
|
.CA_HIT(CA_HIT),
|
.CA_SET(CA_SET),
|
.CA_SET(CA_SET),
|
.WB_ACC(WB_ACC),
|
.WB_ACC(WB_ACC),
|
.USE_CA(USE_CA),
|
.USE_CA(USE_CA),
|
.IOSEL(RADR[31:28]),
|
.IOSEL(RADR[31:28]),
|
.IO_SPACE(IO_SPACE),
|
.IO_SPACE(IO_SPACE),
|
.KILL(KILL),
|
.KILL(KILL),
|
.DC_ILO(RWVAL[2]),
|
.DC_ILO(RWVAL[2]),
|
.UPDATE(UPDATE_C));
|
.UPDATE(UPDATE_C));
|
|
|
DCA_CONTROL DCA_CTRL(
|
DCA_CONTROL DCA_CTRL(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.MCLK(MCLK),
|
.MCLK(MCLK),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.CA_SET(CA_SET),
|
.CA_SET(CA_SET),
|
.HIT_ALL(HIT_ALL),
|
.HIT_ALL(HIT_ALL),
|
.UPDATE(UPDATE_C),
|
.UPDATE(UPDATE_C),
|
.VADR_R(ADDR[11:7]),
|
.VADR_R(ADDR[11:7]),
|
.DRAM_ACC(DRAM_ACC),
|
.DRAM_ACC(DRAM_ACC),
|
.CUPDATE(CUPDATE),
|
.CUPDATE(CUPDATE),
|
.KILL(KILL),
|
.KILL(KILL),
|
.WRITE(WRITE),
|
.WRITE(WRITE),
|
.WRCFG(WRCFG),
|
.WRCFG(WRCFG),
|
.WCTRL(WCTRL[1:0]),
|
.WCTRL(WCTRL[1:0]),
|
.INVAL_A(CINVAL[1]),
|
.INVAL_A(CINVAL[1]),
|
.DAT_CV(DAT_CV),
|
.DAT_CV(DAT_CV),
|
.WADR_CV(WADR_CV),
|
.WADR_CV(WADR_CV),
|
.WE_CV(WE_CV),
|
.WE_CV(WE_CV),
|
.INIT_CA_RUN(INIT_CA_RUN),
|
.INIT_CA_RUN(INIT_CA_RUN),
|
.WRCRAM0(WRCRAM0),
|
.WRCRAM0(WRCRAM0),
|
.WRCRAM1(WRCRAM1),
|
.WRCRAM1(WRCRAM1),
|
.WRSET0(WRSET0),
|
.WRSET0(WRSET0),
|
.WRSET1(WRSET1));
|
.WRSET1(WRSET1));
|
|
|
MMU_MATCH MMU_COMPARE(
|
MMU_MATCH MMU_COMPARE(
|
.USER(USER),
|
.USER(USER),
|
.WRITE(WRITE),
|
.WRITE(WRITE),
|
.READ(READ),
|
.READ(READ),
|
.RMW(RMW),
|
.RMW(RMW),
|
.IVAR(IVAR),
|
.IVAR(IVAR),
|
.MCR_FLAGS(MCR_FLAGS[2:0]),
|
.MCR_FLAGS(MCR_FLAGS[2:0]),
|
.MMU_VA(MMU_Q[35:20]),
|
.MMU_VA(MMU_Q[35:20]),
|
.MVALID(MVALID),
|
.MVALID(MVALID),
|
.VADR_R(VADR_R[31:12]),
|
.VADR_R(VADR_R[31:12]),
|
.MMU_HIT(MMU_HIT),
|
.MMU_HIT(MMU_HIT),
|
.PROT_ERROR(PROT_ERROR),
|
.PROT_ERROR(PROT_ERROR),
|
.VIRTUELL(VIRTUELL),
|
.VIRTUELL(VIRTUELL),
|
.CI(CI),
|
.CI(CI),
|
.SEL_PTB1(SEL_PTB1),
|
.SEL_PTB1(SEL_PTB1),
|
.UPDATE(UPDATE_M));
|
.UPDATE(UPDATE_M));
|
|
|
MMU_UP MMU_CTRL(
|
MMU_UP MMU_CTRL(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.NEW_PTB(NEW_PTB),
|
.NEW_PTB(NEW_PTB),
|
.IVAR(IVAR[1]),
|
.IVAR(IVAR[1]),
|
.PTB1(PTB_ONE),
|
.PTB1(PTB_ONE),
|
.WR_MRAM(WR_MRAM),
|
.WR_MRAM(WR_MRAM),
|
.MVALID(MVALID),
|
.MVALID(MVALID),
|
.UPDATE(UPDATE_M),
|
.UPDATE(UPDATE_M),
|
.VADR(VADR[19:16]),
|
.VADR(VADR[19:16]),
|
.VADR_R(VADR_R[19:16]),
|
.VADR_R(VADR_R[19:16]),
|
.WE_MV(WEMV),
|
.WE_MV(WEMV),
|
.NEW_PTB_RUN(NEW_PTB_RUN),
|
.NEW_PTB_RUN(NEW_PTB_RUN),
|
.DAT_MV(DAT_MV),
|
.DAT_MV(DAT_MV),
|
.RADR_MV(RADR_MV),
|
.RADR_MV(RADR_MV),
|
.WADR_MV(WADR_MV));
|
.WADR_MV(WADR_MV));
|
|
|
// +++++++++++++++++++++++++ MMU Valid +++++++++++++++++++++
|
// +++++++++++++++++++++++++ MMU Valid +++++++++++++++++++++
|
|
|
always @(posedge BCLK) MVALID <= MMU_VALID[RADR_MV];
|
always @(posedge BCLK) MVALID <= MMU_VALID[RADR_MV];
|
|
|
always @(negedge BCLK) if (WEMV) MMU_VALID[WADR_MV] <= DAT_MV;
|
always @(negedge BCLK) if (WEMV) MMU_VALID[WADR_MV] <= DAT_MV;
|
|
|
// +++++++++++++++++++++++++ MMU Tags ++++++++++++++++++++++
|
// +++++++++++++++++++++++++ MMU Tags ++++++++++++++++++++++
|
|
|
always @(posedge BCLK) MMU_Q <= MMU_TAGS[VADR[19:12]];
|
always @(posedge BCLK) MMU_Q <= MMU_TAGS[VADR[19:12]];
|
|
|
always @(negedge BCLK) if (WR_MRAM) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};
|
always @(negedge BCLK) if (WR_MRAM) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};
|
|
|
RD_ALIGNER RD_ALI(
|
RD_ALIGNER RD_ALI(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.ACC_OK(ACC_STAT[0]),
|
.ACC_OK(ACC_STAT[0]),
|
.REG_OUT(REG_OUT),
|
.REG_OUT(REG_OUT),
|
.PACKET(PACKET),
|
.PACKET(PACKET),
|
.RDDATA(LAST_DAT),
|
.RDDATA(LAST_DAT),
|
.SIZE(SIZE),
|
.SIZE(SIZE),
|
.CA_HIT(CA_HIT),
|
.CA_HIT(CA_HIT),
|
.DP_DI(DP_DI),
|
.DP_DI(DP_DI),
|
.AUX_QW(AUX_QW));
|
.AUX_QW(AUX_QW));
|
|
|
WR_ALIGNER WR_ALI(
|
WR_ALIGNER WR_ALI(
|
.DP_Q(DP_Q),
|
.DP_Q(DP_Q),
|
.PACKET(PACKET),
|
.PACKET(PACKET),
|
.SIZE(SIZE),
|
.SIZE(SIZE),
|
.ENBYTE(ENBYTE),
|
.ENBYTE(ENBYTE),
|
.WRDATA(WRDATA));
|
.WRDATA(WRDATA));
|
|
|
DEBUG_AE DBGAE(
|
DEBUG_AE DBGAE(
|
.DBG_IN(DBG_IN),
|
.DBG_IN(DBG_IN),
|
.READ(READ),
|
.READ(READ),
|
.WRITE(WRITE),
|
.WRITE(WRITE),
|
.USER(USER),
|
.USER(USER),
|
.VIRTUELL(VIRTUELL),
|
.VIRTUELL(VIRTUELL),
|
.ACC_OK(ACC_STAT[0]),
|
.ACC_OK(ACC_STAT[0]),
|
.VADR_R(VADR_R[31:2]),
|
.VADR_R(VADR_R[31:2]),
|
.MMU_Q(MMU_Q[19:0]),
|
.MMU_Q(MMU_Q[19:0]),
|
.ENBYTE(ENBYTE),
|
.ENBYTE(ENBYTE),
|
.DBG_HIT(DBG_HIT));
|
.DBG_HIT(DBG_HIT));
|
|
|
endmodule
|
endmodule
|
|
|
