// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: ICACHE.v
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// Filename: ICACHE.v
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// Project: M32632
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// Version: 3.2 bug fix
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// Version: 3.1 bug fix of 25 February 2019
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// History: 3.1 bug fix of 25 February 2019
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// History: 3.0 Cache Interface reworked
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// 3.0 Cache Interface reworked
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// 2.0 50 MHz release of 14 August 2016
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// 2.0 50 MHz release of 14 August 2016
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// 1.0 first release of 30 Mai 2015
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// 1.0 first release of 30 Mai 2015
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// Author: Udo Moeller
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// Date: 17 January 2021
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// Date: 8 July 2017
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//
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//
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// Copyright (C) 2019 Udo Moeller
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// Copyright (C) 2021 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// ICACHE the instruction cache of M32632
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// ICACHE the instruction cache of M32632
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module ICACHE( BCLK, DRAMSZ, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,
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module ICACHE( BCLK, DRAMSZ, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,
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KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, IVAR_MUX, VADR_D, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR_I,
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KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, IVAR_MUX, VADR_D, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR_I,
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INHIBIT, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,
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INHIBIT, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,
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DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );
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DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );
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input BCLK;
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input BCLK;
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input [2:0] DRAMSZ;
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input [2:0] DRAMSZ;
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input MDONE;
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input MDONE;
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input BRESET;
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input BRESET;
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input READ_I;
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input READ_I;
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input IO_READY;
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input IO_READY;
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input PSR_USER;
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input PSR_USER;
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input DATA_HOLD;
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input DATA_HOLD;
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input PTB_WR;
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input PTB_WR;
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input PTB_SEL;
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input PTB_SEL;
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input DRAM_WR;
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input DRAM_WR;
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input KDET;
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input KDET;
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input HOLD;
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input HOLD;
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input [1:0] CFG;
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input [1:0] CFG;
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input [127:0] DRAM_Q;
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input [127:0] DRAM_Q;
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input [1:0] CINVAL;
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input [1:0] CINVAL;
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input [1:0] IC_SIGS;
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input [1:0] IC_SIGS;
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input [31:0] IO_Q;
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input [31:0] IO_Q;
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input [1:0] IVAR;
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input [1:0] IVAR;
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input IVAR_MUX;
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input IVAR_MUX;
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input [31:12] VADR_D;
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input [31:12] VADR_D;
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input [28:4] KOLLI_A;
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input [28:4] KOLLI_A;
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input [3:0] MCR_FLAGS;
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input [3:0] MCR_FLAGS;
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input [23:0] MMU_DIN;
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input [23:0] MMU_DIN;
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input [31:0] VADR_I;
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input [31:0] VADR_I;
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input INHIBIT;
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input INHIBIT;
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input ENA_HK;
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input ENA_HK;
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input ENDRAM;
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input ENDRAM;
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output IO_RD;
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output IO_RD;
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output DRAM_ACC;
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output DRAM_ACC;
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output INIT_RUN;
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output INIT_RUN;
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output PROT_ERROR;
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output PROT_ERROR;
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output ACC_OK;
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output ACC_OK;
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output IC_PREQ;
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output IC_PREQ;
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output KOLLISION;
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output KOLLISION;
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output STOP_CINV;
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output STOP_CINV;
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output [31:0] IC_DQ;
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output [31:0] IC_DQ;
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output [31:12] IC_VA;
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output [31:12] IC_VA;
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output [3:0] ICTODC;
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output [3:0] ICTODC;
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output reg [28:0] DRAM_A;
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output reg [28:0] DRAM_A;
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output reg [31:0] IO_A;
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output reg [31:0] IO_A;
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reg [31:0] VADR_R;
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reg [31:0] VADR_R;
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reg [31:0] CAPDAT;
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reg [31:0] CAPDAT;
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reg [31:0] DFFE_IOR;
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reg [31:0] DFFE_IOR;
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reg HOLD_ON;
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reg HOLD_ON;
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reg DFF_HDFF1;
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reg DFF_HDFF1;
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reg DFF_IRD_REG;
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reg DFF_IRD_REG;
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wire [31:0] VADR;
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wire [31:0] VADR;
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wire [4:0] A_CV;
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wire [4:0] A_CV;
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wire ACOK;
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wire ACOK;
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wire [4:0] ACV;
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wire [4:0] ACV;
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wire AUX_DAT;
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wire AUX_DAT;
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wire CA_HIT;
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wire CA_HIT;
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wire CA_SET;
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wire CA_SET;
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wire CUPDATE;
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wire CUPDATE;
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wire [23:0] D_CV;
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wire [23:0] D_CV;
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wire HIT_ALL;
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wire HIT_ALL;
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wire INIT_CA_RUN;
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wire INIT_CA_RUN;
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wire IO_ACC;
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wire IO_ACC;
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wire KILL;
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wire KILL;
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wire NEW_PTB;
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wire NEW_PTB;
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wire PTB_ONE;
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wire PTB_ONE;
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wire [31:12] RADR;
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wire [31:12] RADR;
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wire READ;
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wire READ;
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wire RUN_ICRD;
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wire RUN_ICRD;
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wire STOP_ICRD;
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wire STOP_ICRD;
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wire [23:0] UPCD;
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wire [23:0] UPCD;
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wire [23:0] UPDATE_C;
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wire [23:0] UPDATE_C;
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wire [31:0] UPDATE_M;
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wire [31:0] UPDATE_M;
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wire USE_CA;
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wire USE_CA;
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wire USER;
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wire USER;
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wire [11:7] V_ADR;
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wire [11:7] V_ADR;
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wire WE_CV;
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wire WE_CV;
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wire WEMV;
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wire WEMV;
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wire WRCRAM0;
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wire WRCRAM0;
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wire WRCRAM1;
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wire WRCRAM1;
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wire WRSET0;
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wire WRSET0;
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wire WRSET1;
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wire WRSET1;
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wire WRITE;
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wire WRITE;
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wire [11:7] KILLADR;
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wire [11:7] KILLADR;
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wire AUX_ALT;
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wire AUX_ALT;
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wire VIRT_A;
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wire VIRT_A;
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wire CI;
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wire CI;
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wire MMU_HIT;
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wire MMU_HIT;
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wire LD_DRAM_A;
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wire LD_DRAM_A;
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wire IO_SPACE;
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wire IO_SPACE;
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wire LAST_MUX;
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wire LAST_MUX;
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wire VIRTUELL;
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wire VIRTUELL;
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wire NEW_PTB_RUN;
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wire NEW_PTB_RUN;
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wire [31:0] SET_DAT;
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wire [31:0] SET_DAT;
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wire [31:0] ALT_DAT;
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wire [31:0] ALT_DAT;
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wire [31:0] DAT_MV;
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wire [31:0] DAT_MV;
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wire [3:0] RADR_MV;
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wire [3:0] RADR_MV;
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wire [3:0] WADR_MV;
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wire [3:0] WADR_MV;
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wire [23:0] NEWCVAL;
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wire [23:0] NEWCVAL;
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wire KILL_C,KILL_K;
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wire KILL_C,KILL_K;
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wire RMW;
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wire RMW;
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wire [31:0] CAP_Q;
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wire [31:0] CAP_Q;
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wire [28:12] TAGDAT;
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wire [28:12] TAGDAT;
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wire clr_up;
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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// +++++++++++++++++++ Memories ++++++++++++++++++++
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reg [127:0] DATA0 [0:255]; // Data Set 0 : 4 kBytes
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reg [127:0] DATA0 [0:255]; // Data Set 0 : 4 kBytes
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reg [127:0] RDDATA0;
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reg [127:0] RDDATA0;
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reg [31:0] SET_DAT0;
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reg [31:0] SET_DAT0;
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reg [127:0] DATA1 [0:255]; // Data Set 1 : 4 kBytes
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reg [127:0] DATA1 [0:255]; // Data Set 1 : 4 kBytes
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reg [127:0] RDDATA1;
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reg [127:0] RDDATA1;
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reg [31:0] SET_DAT1;
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reg [31:0] SET_DAT1;
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reg [16:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 17 bits
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reg [16:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 17 bits
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reg [16:0] TAG0;
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reg [16:0] TAG0;
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reg [16:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 17 bits
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reg [16:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 17 bits
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reg [16:0] TAG1;
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reg [16:0] TAG1;
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wire [23:0] CVALID;
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wire [23:0] CVALID;
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reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
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reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
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reg [35:0] MMU_Q;
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reg [35:0] MMU_Q;
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reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
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reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
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reg [31:0] MVALID;
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reg [31:0] MVALID;
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reg [16:0] KTAGSET_0 [0:255]; // Kollision Tag Set for Data Set 0 : 256 entries of 17 bits
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reg [16:0] KTAGSET_0 [0:255]; // Kollision Tag Set for Data Set 0 : 256 entries of 17 bits
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reg [16:0] KTAG0;
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reg [16:0] KTAG0;
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reg [16:0] KTAGSET_1 [0:255]; // Kollision Tag Set for Data Set 1 : 256 entries of 17 bits
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reg [16:0] KTAGSET_1 [0:255]; // Kollision Tag Set for Data Set 1 : 256 entries of 17 bits
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reg [16:0] KTAG1;
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reg [16:0] KTAG1;
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wire [23:0] KCVALID;
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wire [23:0] KCVALID;
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assign READ = READ_I & ~HOLD_ON & RUN_ICRD;
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assign READ = READ_I & ~HOLD_ON & RUN_ICRD;
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assign WRITE = 1'b0;
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assign WRITE = 1'b0;
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assign RMW = 1'b0;
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assign RMW = 1'b0;
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assign ALT_DAT = AUX_ALT ? DFFE_IOR : CAPDAT ;
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assign ALT_DAT = AUX_ALT ? DFFE_IOR : CAPDAT ;
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assign RADR = VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;
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assign RADR = VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;
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assign V_ADR = STOP_ICRD ? KILLADR : VADR[11:7] ;
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assign V_ADR = STOP_ICRD ? KILLADR : VADR[11:7] ;
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assign ACV = STOP_ICRD ? KILLADR : A_CV ;
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assign ACV = STOP_ICRD ? KILLADR : A_CV ;
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assign UPCD = STOP_ICRD ? NEWCVAL : UPDATE_C ;
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assign UPCD = STOP_ICRD ? NEWCVAL : UPDATE_C ;
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assign IC_DQ = LAST_MUX ? ALT_DAT : SET_DAT ;
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assign IC_DQ = LAST_MUX ? ALT_DAT : SET_DAT ;
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assign SET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;
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assign SET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;
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assign KILL = KILL_C | KILL_K;
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assign KILL = KILL_C | KILL_K;
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assign IC_VA = VADR_R[31:12];
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assign IC_VA = VADR_R[31:12];
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assign VIRT_A = ~CINVAL[0] & VIRTUELL;
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assign VIRT_A = ~CINVAL[0] & VIRTUELL;
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assign ACC_OK = HOLD_ON | ACOK;
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assign ACC_OK = HOLD_ON | ACOK;
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assign USER = ~MCR_FLAGS[3] & PSR_USER;
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assign USER = ~MCR_FLAGS[3] & PSR_USER;
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assign AUX_ALT = HOLD_ON | DFF_IRD_REG;
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assign AUX_ALT = HOLD_ON | DFF_IRD_REG;
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assign LAST_MUX = AUX_ALT | AUX_DAT;
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assign LAST_MUX = AUX_ALT | AUX_DAT;
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assign INIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;
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assign INIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;
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assign LD_DRAM_A = ~DRAM_ACC | MDONE;
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assign LD_DRAM_A = ~DRAM_ACC | MDONE;
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assign ICTODC[3] = USER;
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assign ICTODC[3] = USER;
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assign VADR[31:12] = IVAR_MUX ? VADR_D : VADR_I[31:12];
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assign VADR[31:12] = IVAR_MUX ? VADR_D : VADR_I[31:12];
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assign VADR[11:0] = VADR_I[11:0];
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assign VADR[11:0] = VADR_I[11:0];
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always @(posedge BCLK) VADR_R <= VADR;
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always @(posedge BCLK) VADR_R[23:0] <= VADR[23:0];
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assign clr_up = ~(DRAMSZ == 3'd0);
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always @(posedge BCLK or negedge clr_up)
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if (!clr_up) VADR_R[31:24] <= 8'd0;
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else VADR_R[31:24] <= VADR[31:24];
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always @(posedge BCLK) DFF_IRD_REG <= IO_RD;
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always @(posedge BCLK) DFF_IRD_REG <= IO_RD;
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always @(posedge BCLK) DFF_HDFF1 <= IO_READY;
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always @(posedge BCLK) DFF_HDFF1 <= IO_READY;
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always @(posedge BCLK) if (LD_DRAM_A) DRAM_A <= {RADR[28:12],VADR_R[11:2],USE_CA,CA_SET};
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always @(posedge BCLK) if (LD_DRAM_A) DRAM_A <= {RADR[28:12],VADR_R[11:2],USE_CA,CA_SET};
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always @(posedge BCLK) if (IO_ACC) IO_A <= {RADR[31:12],VADR_R[11:0]};
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always @(posedge BCLK) if (IO_ACC) IO_A <= {RADR[31:12],VADR_R[11:0]};
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always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
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always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) HOLD_ON <= 1'b0;
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if (!BRESET) HOLD_ON <= 1'b0;
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else HOLD_ON <= (DATA_HOLD & DFF_HDFF1) | (HOLD_ON & DATA_HOLD);
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else HOLD_ON <= (DATA_HOLD & DFF_HDFF1) | (HOLD_ON & DATA_HOLD);
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DMUX DMUX_4TO1 (
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DMUX DMUX_4TO1 (
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.DRAM_Q(DRAM_Q),
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.DRAM_Q(DRAM_Q),
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.ADDR(VADR_R[3:2]),
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.ADDR(VADR_R[3:2]),
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.CAP_Q(CAP_Q) );
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.CAP_Q(CAP_Q) );
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always @(posedge BCLK) if (MDONE) CAPDAT <= CAP_Q;
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always @(posedge BCLK) if (MDONE) CAPDAT <= CAP_Q;
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FILTCMP FILT_CMP(
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FILTCMP FILT_CMP(
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.RADR({RADR[28:12],VADR_R[11:4]}),
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.RADR({RADR[28:12],VADR_R[11:4]}),
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.DRAMSZ(DRAMSZ),
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.DRAMSZ(DRAMSZ),
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.DRAM_A(25'd0),
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.DRAM_A(25'd0),
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.TAGDAT(TAGDAT),
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.TAGDAT(TAGDAT),
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.ADR_EQU());
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.ADR_EQU());
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// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
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// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
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NEU_VALID VALID_RAM(
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NEU_VALID VALID_RAM(
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.BCLK(BCLK),
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.BCLK(BCLK),
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.VALIN(D_CV),
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.VALIN(D_CV),
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.WADR(ACV),
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.WADR(ACV),
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.WREN(WE_CV),
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.WREN(WE_CV),
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.RADR(V_ADR[11:7]),
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.RADR(V_ADR[11:7]),
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.VALOUT(CVALID) );
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.VALOUT(CVALID) );
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// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
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// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
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always @(posedge BCLK) TAG0 <= TAGSET_0[VADR[11:4]];
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always @(posedge BCLK) TAG0 <= TAGSET_0[VADR[11:4]];
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always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= TAGDAT;
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always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= TAGDAT;
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// +++++++++++++++++++++++++ Tag Set 1 +++++++++++++++++++++
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// +++++++++++++++++++++++++ Tag Set 1 +++++++++++++++++++++
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always @(posedge BCLK) TAG1 <= TAGSET_1[VADR[11:4]];
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always @(posedge BCLK) TAG1 <= TAGSET_1[VADR[11:4]];
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always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= TAGDAT;
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always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= TAGDAT;
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// +++++++++++++++++++++++++ Data Set 0 ++++++++++++++++++++
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// +++++++++++++++++++++++++ Data Set 0 ++++++++++++++++++++
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always @(posedge BCLK) RDDATA0 <= DATA0[VADR[11:4]];
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always @(posedge BCLK) RDDATA0 <= DATA0[VADR[11:4]];
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always @(RDDATA0 or VADR_R)
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always @(RDDATA0 or VADR_R)
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case (VADR_R[3:2])
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case (VADR_R[3:2])
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2'b00 : SET_DAT0 <= RDDATA0[31:0];
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2'b00 : SET_DAT0 <= RDDATA0[31:0];
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2'b01 : SET_DAT0 <= RDDATA0[63:32];
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2'b01 : SET_DAT0 <= RDDATA0[63:32];
|
2'b10 : SET_DAT0 <= RDDATA0[95:64];
|
2'b10 : SET_DAT0 <= RDDATA0[95:64];
|
2'b11 : SET_DAT0 <= RDDATA0[127:96];
|
2'b11 : SET_DAT0 <= RDDATA0[127:96];
|
endcase
|
endcase
|
|
|
always @(posedge BCLK) if (WRSET0) DATA0[VADR_R[11:4]] <= DRAM_Q;
|
always @(posedge BCLK) if (WRSET0) DATA0[VADR_R[11:4]] <= DRAM_Q;
|
|
|
// +++++++++++++++++++++++++ Data Set 1 ++++++++++++++++++++
|
// +++++++++++++++++++++++++ Data Set 1 ++++++++++++++++++++
|
|
|
always @(posedge BCLK) RDDATA1 <= DATA1[VADR[11:4]];
|
always @(posedge BCLK) RDDATA1 <= DATA1[VADR[11:4]];
|
|
|
always @(RDDATA1 or VADR_R)
|
always @(RDDATA1 or VADR_R)
|
case (VADR_R[3:2])
|
case (VADR_R[3:2])
|
2'b00 : SET_DAT1 <= RDDATA1[31:0];
|
2'b00 : SET_DAT1 <= RDDATA1[31:0];
|
2'b01 : SET_DAT1 <= RDDATA1[63:32];
|
2'b01 : SET_DAT1 <= RDDATA1[63:32];
|
2'b10 : SET_DAT1 <= RDDATA1[95:64];
|
2'b10 : SET_DAT1 <= RDDATA1[95:64];
|
2'b11 : SET_DAT1 <= RDDATA1[127:96];
|
2'b11 : SET_DAT1 <= RDDATA1[127:96];
|
endcase
|
endcase
|
|
|
always @(posedge BCLK) if (WRSET1) DATA1[VADR_R[11:4]] <= DRAM_Q;
|
always @(posedge BCLK) if (WRSET1) DATA1[VADR_R[11:4]] <= DRAM_Q;
|
|
|
CA_MATCH DCA_COMPARE(
|
CA_MATCH DCA_COMPARE(
|
.INVAL_L(CINVAL[0]),
|
.INVAL_L(CINVAL[0]),
|
.CI(CI),
|
.CI(CI),
|
.MMU_HIT(MMU_HIT),
|
.MMU_HIT(MMU_HIT),
|
.WRITE(WRITE),
|
.WRITE(WRITE),
|
.KDET(1'b0),
|
.KDET(1'b0),
|
.ADDR({RADR[31:12],VADR_R[11:4]}),
|
.ADDR({RADR[31:12],VADR_R[11:4]}),
|
.CFG(CFG),
|
.CFG(CFG),
|
.ENDRAM(ENDRAM),
|
.ENDRAM(ENDRAM),
|
.CVALID(CVALID),
|
.CVALID(CVALID),
|
.TAG0(TAG0),
|
.TAG0(TAG0),
|
.TAG1(TAG1),
|
.TAG1(TAG1),
|
.CA_HIT(CA_HIT),
|
.CA_HIT(CA_HIT),
|
.CA_SET(CA_SET),
|
.CA_SET(CA_SET),
|
.WB_ACC(),
|
.WB_ACC(),
|
.USE_CA(USE_CA),
|
.USE_CA(USE_CA),
|
.DRAMSZ(DRAMSZ),
|
.DRAMSZ(DRAMSZ),
|
.IO_SPACE(IO_SPACE),
|
.IO_SPACE(IO_SPACE),
|
.DC_ILO(1'b0),
|
.DC_ILO(1'b0),
|
.KILL(KILL_C),
|
.KILL(KILL_C),
|
.UPDATE(UPDATE_C));
|
.UPDATE(UPDATE_C));
|
|
|
DCA_CONTROL DCA_CTRL(
|
DCA_CONTROL DCA_CTRL(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.CA_SET(CA_SET),
|
.CA_SET(CA_SET),
|
.HIT_ALL(HIT_ALL),
|
.HIT_ALL(HIT_ALL),
|
.UPDATE(UPCD),
|
.UPDATE(UPCD),
|
.VADR_R(VADR_R[11:7]),
|
.VADR_R(VADR_R[11:7]),
|
.DRAM_ACC(DRAM_ACC),
|
.DRAM_ACC(DRAM_ACC),
|
.CUPDATE(CUPDATE),
|
.CUPDATE(CUPDATE),
|
.KILL(KILL),
|
.KILL(KILL),
|
.WRITE(WRITE),
|
.WRITE(WRITE),
|
.USE_CA(DRAM_A[1]),
|
.USE_CA(DRAM_A[1]),
|
.INHIBIT(INHIBIT),
|
.INHIBIT(INHIBIT),
|
.INVAL_A(CINVAL[1]),
|
.INVAL_A(CINVAL[1]),
|
.MDONE(MDONE),
|
.MDONE(MDONE),
|
.DAT_CV(D_CV),
|
.DAT_CV(D_CV),
|
.WADR_CV(A_CV),
|
.WADR_CV(A_CV),
|
.WE_CV(WE_CV),
|
.WE_CV(WE_CV),
|
.INIT_CA_RUN(INIT_CA_RUN),
|
.INIT_CA_RUN(INIT_CA_RUN),
|
.WRCRAM0(WRCRAM0),
|
.WRCRAM0(WRCRAM0),
|
.WRCRAM1(WRCRAM1),
|
.WRCRAM1(WRCRAM1),
|
.WRSET0(WRSET0),
|
.WRSET0(WRSET0),
|
.WRSET1(WRSET1));
|
.WRSET1(WRSET1));
|
|
|
ICACHE_SM IC_SM(
|
ICACHE_SM IC_SM(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.IO_SPACE(IO_SPACE),
|
.IO_SPACE(IO_SPACE),
|
.READ(READ),
|
.READ(READ),
|
.MDONE(MDONE),
|
.MDONE(MDONE),
|
.IO_READY(IO_READY),
|
.IO_READY(IO_READY),
|
.MMU_HIT(MMU_HIT),
|
.MMU_HIT(MMU_HIT),
|
.CA_HIT(CA_HIT),
|
.CA_HIT(CA_HIT),
|
.USE_CA(USE_CA),
|
.USE_CA(USE_CA),
|
.PTB_WR(PTB_WR),
|
.PTB_WR(PTB_WR),
|
.PTB_SEL(PTB_SEL),
|
.PTB_SEL(PTB_SEL),
|
.USER(USER),
|
.USER(USER),
|
.PROT_ERROR(PROT_ERROR),
|
.PROT_ERROR(PROT_ERROR),
|
.PTE_ACC(IC_SIGS[1]),
|
.PTE_ACC(IC_SIGS[1]),
|
.ACC_OK(ACOK),
|
.ACC_OK(ACOK),
|
.PTB_ONE(PTB_ONE),
|
.PTB_ONE(PTB_ONE),
|
.NEW_PTB(NEW_PTB),
|
.NEW_PTB(NEW_PTB),
|
.AUX_DAT(AUX_DAT),
|
.AUX_DAT(AUX_DAT),
|
.CUPDATE(CUPDATE),
|
.CUPDATE(CUPDATE),
|
.IO_RD(IO_RD),
|
.IO_RD(IO_RD),
|
.IO_ACC(IO_ACC),
|
.IO_ACC(IO_ACC),
|
.DRAM_ACC(DRAM_ACC),
|
.DRAM_ACC(DRAM_ACC),
|
.IC_PREQ(IC_PREQ),
|
.IC_PREQ(IC_PREQ),
|
.HIT_ALL(HIT_ALL));
|
.HIT_ALL(HIT_ALL));
|
|
|
// +++++++++++++++++++++++++ Kollision Valid +++++++++++++++
|
// +++++++++++++++++++++++++ Kollision Valid +++++++++++++++
|
|
|
NEU_VALID KOL_VAL(
|
NEU_VALID KOL_VAL(
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.VALIN(D_CV),
|
.VALIN(D_CV),
|
.WADR(ACV),
|
.WADR(ACV),
|
.WREN(WE_CV),
|
.WREN(WE_CV),
|
.RADR(KOLLI_A[11:7]),
|
.RADR(KOLLI_A[11:7]),
|
.VALOUT(KCVALID) );
|
.VALOUT(KCVALID) );
|
|
|
// +++++++++++++++++++++++++ Kollision Tag Set 0 +++++++++++
|
// +++++++++++++++++++++++++ Kollision Tag Set 0 +++++++++++
|
|
|
always @(posedge BCLK) KTAG0 <= KTAGSET_0[KOLLI_A[11:4]];
|
always @(posedge BCLK) KTAG0 <= KTAGSET_0[KOLLI_A[11:4]];
|
|
|
always @(negedge BCLK) if (WRCRAM0) KTAGSET_0[VADR_R[11:4]] <= TAGDAT;
|
always @(negedge BCLK) if (WRCRAM0) KTAGSET_0[VADR_R[11:4]] <= TAGDAT;
|
|
|
// +++++++++++++++++++++++++ Kollision Tag Set 1 +++++++++++
|
// +++++++++++++++++++++++++ Kollision Tag Set 1 +++++++++++
|
|
|
always @(posedge BCLK) KTAG1 <= KTAGSET_1[KOLLI_A[11:4]];
|
always @(posedge BCLK) KTAG1 <= KTAGSET_1[KOLLI_A[11:4]];
|
|
|
always @(negedge BCLK) if (WRCRAM1) KTAGSET_1[VADR_R[11:4]] <= TAGDAT;
|
always @(negedge BCLK) if (WRCRAM1) KTAGSET_1[VADR_R[11:4]] <= TAGDAT;
|
|
|
KOLDETECT KOLLOGIK(
|
KOLDETECT KOLLOGIK(
|
.DRAM_WR(DRAM_WR),
|
.DRAM_WR(DRAM_WR),
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.READ_I(READ_I),
|
.READ_I(READ_I),
|
.ACC_OK(ACC_OK),
|
.ACC_OK(ACC_OK),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.INVAL_A(CINVAL[1]),
|
.INVAL_A(CINVAL[1]),
|
.KDET(KDET),
|
.KDET(KDET),
|
.HOLD(HOLD),
|
.HOLD(HOLD),
|
.ENA_HK(ENA_HK),
|
.ENA_HK(ENA_HK),
|
.STOP_CINV(STOP_CINV),
|
.STOP_CINV(STOP_CINV),
|
.ADDR(KOLLI_A),
|
.ADDR(KOLLI_A),
|
.C_VALID(KCVALID),
|
.C_VALID(KCVALID),
|
.CFG(CFG),
|
.CFG(CFG),
|
.CVALID(CVALID),
|
.CVALID(CVALID),
|
.TAG0(KTAG0),
|
.TAG0(KTAG0),
|
.TAG1(KTAG1),
|
.TAG1(KTAG1),
|
.KOLLISION(KOLLISION),
|
.KOLLISION(KOLLISION),
|
.STOP_ICRD(STOP_ICRD),
|
.STOP_ICRD(STOP_ICRD),
|
.RUN_ICRD(RUN_ICRD),
|
.RUN_ICRD(RUN_ICRD),
|
.KILL(KILL_K),
|
.KILL(KILL_K),
|
.ICTODC(ICTODC[2:0]),
|
.ICTODC(ICTODC[2:0]),
|
.KILLADR(KILLADR),
|
.KILLADR(KILLADR),
|
.NEWCVAL(NEWCVAL));
|
.NEWCVAL(NEWCVAL));
|
|
|
MMU_MATCH MMU_COMPARE(
|
MMU_MATCH MMU_COMPARE(
|
.USER(USER),
|
.USER(USER),
|
.READ(READ),
|
.READ(READ),
|
.WRITE(WRITE),
|
.WRITE(WRITE),
|
.RMW(RMW),
|
.RMW(RMW),
|
.IVAR(IVAR),
|
.IVAR(IVAR),
|
.MCR_FLAGS(MCR_FLAGS[2:0]),
|
.MCR_FLAGS(MCR_FLAGS[2:0]),
|
.MMU_VA(MMU_Q[35:20]),
|
.MMU_VA(MMU_Q[35:20]),
|
.MVALID(MVALID),
|
.MVALID(MVALID),
|
.VADR_R(VADR_R[31:12]),
|
.VADR_R(VADR_R[31:12]),
|
.MMU_HIT(MMU_HIT),
|
.MMU_HIT(MMU_HIT),
|
.PROT_ERROR(PROT_ERROR),
|
.PROT_ERROR(PROT_ERROR),
|
.VIRTUELL(VIRTUELL),
|
.VIRTUELL(VIRTUELL),
|
.CI(CI),
|
.CI(CI),
|
.SEL_PTB1(),
|
.SEL_PTB1(),
|
.UPDATE(UPDATE_M));
|
.UPDATE(UPDATE_M));
|
|
|
MMU_UP MMU_CTRL(
|
MMU_UP MMU_CTRL(
|
.NEW_PTB(NEW_PTB),
|
.NEW_PTB(NEW_PTB),
|
.IVAR(IVAR[1]),
|
.IVAR(IVAR[1]),
|
.BRESET(BRESET),
|
.BRESET(BRESET),
|
.PTB1(PTB_ONE),
|
.PTB1(PTB_ONE),
|
.BCLK(BCLK),
|
.BCLK(BCLK),
|
.WR_MRAM(IC_SIGS[0]),
|
.WR_MRAM(IC_SIGS[0]),
|
.MVALID(MVALID),
|
.MVALID(MVALID),
|
.UPDATE(UPDATE_M),
|
.UPDATE(UPDATE_M),
|
.VADR(VADR[19:16]),
|
.VADR(VADR[19:16]),
|
.VADR_R(VADR_R[19:16]),
|
.VADR_R(VADR_R[19:16]),
|
.WE_MV(WEMV),
|
.WE_MV(WEMV),
|
.NEW_PTB_RUN(NEW_PTB_RUN),
|
.NEW_PTB_RUN(NEW_PTB_RUN),
|
.DAT_MV(DAT_MV),
|
.DAT_MV(DAT_MV),
|
.RADR_MV(RADR_MV),
|
.RADR_MV(RADR_MV),
|
.WADR_MV(WADR_MV));
|
.WADR_MV(WADR_MV));
|
|
|
// +++++++++++++++++++++++++ MMU Valid +++++++++++++++++++++
|
// +++++++++++++++++++++++++ MMU Valid +++++++++++++++++++++
|
|
|
always @(posedge BCLK) MVALID <= MMU_VALID[RADR_MV];
|
always @(posedge BCLK) MVALID <= MMU_VALID[RADR_MV];
|
|
|
always @(negedge BCLK) if (WEMV) MMU_VALID[WADR_MV] <= DAT_MV;
|
always @(negedge BCLK) if (WEMV) MMU_VALID[WADR_MV] <= DAT_MV;
|
|
|
// +++++++++++++++++++++++++ MMU Tags ++++++++++++++++++++++
|
// +++++++++++++++++++++++++ MMU Tags ++++++++++++++++++++++
|
|
|
always @(posedge BCLK) MMU_Q <= MMU_TAGS[VADR[19:12]];
|
always @(posedge BCLK) MMU_Q <= MMU_TAGS[VADR[19:12]];
|
|
|
always @(negedge BCLK) if (IC_SIGS[0]) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};
|
always @(negedge BCLK) if (IC_SIGS[0]) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};
|
|
|
endmodule
|
endmodule
|
|
|
