// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: ICACHE_SM.v
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// Filename: ICACHE_SM.v
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// Version: 2.0
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// Version: 3.0
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// History: 1.0 first release of 30 Mai 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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// Date: 2 December 2018
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//
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//
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// Copyright (C) 2016 Udo Moeller
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// Copyright (C) 2018 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// 1. KOLDETECT Collision Detection Unit
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// 1. KOLDETECT Collision Detection Unit
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// 2. ICACHE_SM Instruction Cache State Machine
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// 2. DMUX Data Multiplexor
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// 3. ICACHE_SM Instruction Cache State Machine
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 1. KOLDETECT Collision Detection Unit
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// 1. KOLDETECT Collision Detection Unit
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module KOLDETECT ( BCLK, BRESET, DRAM_WR, CVALID, ADDR, TAG0, TAG1 , CFG , C_VALID, READ_I, ACC_OK, HOLD, KDET, INVAL_A, ENA_HK,
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module KOLDETECT ( BCLK, BRESET, DRAM_WR, CVALID, ADDR, TAG0, TAG1 , CFG , C_VALID, READ_I, ACC_OK, HOLD, KDET, INVAL_A, ENA_HK,
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NEWCVAL, KOLLISION, STOP_ICRD, RUN_ICRD, KILL, KILLADR, ICTODC, STOP_CINV );
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NEWCVAL, KOLLISION, STOP_ICRD, RUN_ICRD, KILL, KILLADR, ICTODC, STOP_CINV );
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input BCLK;
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input BCLK;
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input BRESET;
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input BRESET;
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input DRAM_WR;
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input DRAM_WR;
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input [23:0] CVALID; // Data from master Valid RAM
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input [23:0] CVALID; // Data from master Valid RAM
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input [27:4] ADDR;
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input [28:4] ADDR;
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input [27:12] TAG0,TAG1;
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input [28:12] TAG0,TAG1;
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input [1:0] CFG;
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input [1:0] CFG;
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input [23:0] C_VALID; // Data from secondary Valid RAM
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input [23:0] C_VALID; // Data from secondary Valid RAM
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input READ_I;
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input READ_I;
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input ACC_OK;
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input ACC_OK;
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input HOLD; // active low
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input HOLD; // active low
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input KDET;
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input KDET;
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input INVAL_A; // Cache Invalidate All
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input INVAL_A; // Cache Invalidate All
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input ENA_HK; // Enable HOLD and Kohaerenz
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input ENA_HK; // Enable HOLD and Kohaerenz
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output [23:0] NEWCVAL;
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output [23:0] NEWCVAL;
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output KOLLISION;
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output KOLLISION;
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output STOP_ICRD;
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output STOP_ICRD;
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output RUN_ICRD;
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output RUN_ICRD;
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output KILL;
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output KILL;
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output [11:7] KILLADR;
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output [11:7] KILLADR;
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output [2:0] ICTODC;
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output [2:0] ICTODC;
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output STOP_CINV;
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output STOP_CINV;
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reg [27:4] addr_r;
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reg [28:4] addr_r;
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reg [7:0] clear;
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reg [7:0] clear;
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reg do_koll;
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reg do_koll;
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reg [2:0] counter;
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reg [2:0] counter;
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reg [1:0] wpointer,rpointer;
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reg [1:0] wpointer,rpointer;
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reg [35:0] adrfifo;
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reg [35:0] adrfifo;
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reg [8:0] fifo_q,fifo_c;
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reg [8:0] fifo_q,fifo_c;
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reg [1:0] state;
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reg [1:0] state;
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reg pipe;
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reg pipe;
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reg do_kill;
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reg do_kill;
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reg dma;
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reg dma;
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wire [7:0] set_0,set_1;
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wire [7:0] set_0,set_1;
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wire match_0,match_1;
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wire match_0,match_1;
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wire valid_0,valid_1;
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wire valid_0,valid_1;
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wire found_0,found_1;
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wire found_0,found_1;
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wire kolli,dma_kolli;
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wire kolli,dma_kolli;
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wire last_match;
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wire last_match;
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wire wr_entry;
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wire wr_entry;
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wire [23:0] cdaten;
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wire [23:0] cdaten;
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wire [8:0] kaddr;
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wire [8:0] kaddr;
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wire [7:0] new_0,new_1;
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wire [7:0] new_0,new_1;
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wire dma_mode,ic_dma;
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wire dma_mode,ic_dma;
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wire free,ende;
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wire free,ende;
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wire init_b;
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wire init_b;
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always @(posedge BCLK) do_koll <= DRAM_WR & CFG[0]; // one cycle pulse, without Cache Enable no collision
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always @(posedge BCLK) do_koll <= DRAM_WR & CFG[0]; // one cycle pulse, without Cache Enable no collision
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always @(posedge BCLK) addr_r <= ADDR;
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always @(posedge BCLK) addr_r <= ADDR;
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// similar logic like in CA_MATCH
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// similar logic like in CA_MATCH
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assign set_0 = C_VALID[7:0];
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assign set_0 = C_VALID[7:0];
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assign set_1 = C_VALID[15:8];
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assign set_1 = C_VALID[15:8];
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assign valid_0 = set_0[addr_r[6:4]];
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assign valid_0 = set_0[addr_r[6:4]];
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assign valid_1 = set_1[addr_r[6:4]];
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assign valid_1 = set_1[addr_r[6:4]];
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assign match_0 = ( TAG0 == addr_r[27:12] ); // 4KB
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assign match_0 = ( TAG0 == addr_r[28:12] ); // 4KB
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assign match_1 = ( TAG1 == addr_r[27:12] ); // 4KB
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assign match_1 = ( TAG1 == addr_r[28:12] ); // 4KB
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assign found_0 = valid_0 & match_0;
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assign found_0 = valid_0 & match_0;
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assign found_1 = valid_1 & match_1;
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assign found_1 = valid_1 & match_1;
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assign kolli = (found_0 | found_1) & ~CFG[1] & do_koll; // Action only if ICACHE is not locked
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assign kolli = (found_0 | found_1) & ~CFG[1] & do_koll; // Action only if ICACHE is not locked
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assign KOLLISION = (found_0 | found_1) & do_koll; // to Statistik Modul, Register there
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assign KOLLISION = (found_0 | found_1) & do_koll; // to Statistik Modul, Register there
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assign dma_kolli = (found_0 | found_1) & ~CFG[1] & CFG[0];
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assign dma_kolli = (found_0 | found_1) & ~CFG[1] & CFG[0];
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// the FIFO with 4 entries :
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// the FIFO with 4 entries :
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assign init_b = CFG[0] & ~INVAL_A; // initialise if CINV A too
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assign init_b = CFG[0] & ~INVAL_A; // initialise if CINV A too
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (!init_b) wpointer <= 2'b00;
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if (!init_b) wpointer <= 2'b00;
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else
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else
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wpointer <= wpointer + {1'b0,wr_entry};
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wpointer <= wpointer + {1'b0,wr_entry};
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (!init_b) rpointer <= 2'b00;
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if (!init_b) rpointer <= 2'b00;
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else
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else
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rpointer <= rpointer + {1'b0,do_kill};
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rpointer <= rpointer + {1'b0,do_kill};
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always @(posedge BCLK)
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always @(posedge BCLK)
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begin
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begin
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if (wr_entry && (wpointer == 2'b00)) adrfifo[8:0] <= {addr_r[11:4],found_1};
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if (wr_entry && (wpointer == 2'b00)) adrfifo[8:0] <= {addr_r[11:4],found_1};
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if (wr_entry && (wpointer == 2'b01)) adrfifo[17:9] <= {addr_r[11:4],found_1};
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if (wr_entry && (wpointer == 2'b01)) adrfifo[17:9] <= {addr_r[11:4],found_1};
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if (wr_entry && (wpointer == 2'b10)) adrfifo[26:18] <= {addr_r[11:4],found_1};
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if (wr_entry && (wpointer == 2'b10)) adrfifo[26:18] <= {addr_r[11:4],found_1};
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if (wr_entry && (wpointer == 2'b11)) adrfifo[35:27] <= {addr_r[11:4],found_1};
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if (wr_entry && (wpointer == 2'b11)) adrfifo[35:27] <= {addr_r[11:4],found_1};
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end
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end
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always @(adrfifo or rpointer)
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always @(adrfifo or rpointer)
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case (rpointer)
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case (rpointer)
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2'b00 : fifo_q = adrfifo[8:0];
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2'b00 : fifo_q = adrfifo[8:0];
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2'b01 : fifo_q = adrfifo[17:9];
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2'b01 : fifo_q = adrfifo[17:9];
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2'b10 : fifo_q = adrfifo[26:18];
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2'b10 : fifo_q = adrfifo[26:18];
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2'b11 : fifo_q = adrfifo[35:27];
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2'b11 : fifo_q = adrfifo[35:27];
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endcase
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endcase
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always @(adrfifo or wpointer) // for Match of last entry use wpointer
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always @(adrfifo or wpointer) // for Match of last entry use wpointer
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case (wpointer)
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case (wpointer)
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2'b01 : fifo_c = adrfifo[8:0];
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2'b01 : fifo_c = adrfifo[8:0];
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2'b10 : fifo_c = adrfifo[17:9];
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2'b10 : fifo_c = adrfifo[17:9];
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2'b11 : fifo_c = adrfifo[26:18];
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2'b11 : fifo_c = adrfifo[26:18];
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2'b00 : fifo_c = adrfifo[35:27];
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2'b00 : fifo_c = adrfifo[35:27];
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endcase
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endcase
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// Control
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// Control
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assign last_match = counter[2] & (fifo_c == {addr_r[11:4],found_1}); // if Match with last Entry no new Entry
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assign last_match = counter[2] & (fifo_c == {addr_r[11:4],found_1}); // if Match with last Entry no new Entry
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assign wr_entry = kolli & ~last_match;
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assign wr_entry = kolli & ~last_match;
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always @(posedge BCLK)
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always @(posedge BCLK)
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casex ({init_b,wr_entry,do_kill,counter})
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casex ({init_b,wr_entry,do_kill,counter})
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6'b0_xx_xxx : counter <= 3'b000;
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6'b0_xx_xxx : counter <= 3'b000;
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6'b1_00_xxx : counter <= counter;
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6'b1_00_xxx : counter <= counter;
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6'b1_11_xxx : counter <= counter;
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6'b1_11_xxx : counter <= counter;
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6'b1_10_000 : counter <= 3'b100;
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6'b1_10_000 : counter <= 3'b100;
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6'b1_10_1xx : counter <= (counter[1:0] == 2'b11) ? 3'b111 : {counter[2],(counter[1:0] + 2'b01)}; // Overflow avoid
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6'b1_10_1xx : counter <= (counter[1:0] == 2'b11) ? 3'b111 : {counter[2],(counter[1:0] + 2'b01)}; // Overflow avoid
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6'b1_01_1xx : counter <= (counter[1:0] == 2'b00) ? 3'b000 : {counter[2],(counter[1:0] + 2'b11)};
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6'b1_01_1xx : counter <= (counter[1:0] == 2'b00) ? 3'b000 : {counter[2],(counter[1:0] + 2'b11)};
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default : counter <= counter;
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default : counter <= counter;
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endcase
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endcase
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// DMA Access
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// DMA Access
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always @(posedge BCLK) dma <= ~HOLD; // there is only one FF for this , from here to DCACHE
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always @(posedge BCLK) dma <= ~HOLD; // there is only one FF for this , from here to DCACHE
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// Controlling of ICACHE
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// Controlling of ICACHE
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assign free = (~READ_I | ACC_OK) & ENA_HK; // switch off if CINV
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assign free = (~READ_I | ACC_OK) & ENA_HK; // switch off if CINV
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always @(posedge BCLK) // state[1] state[0]
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always @(posedge BCLK) // state[1] state[0]
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casex ({BRESET,dma,counter[2],free,ende,STOP_ICRD,dma_mode})
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casex ({BRESET,dma,counter[2],free,ende,STOP_ICRD,dma_mode})
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7'b0_xx_xx_xx : state <= 2'b00;
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7'b0_xx_xx_xx : state <= 2'b00;
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7'b1_00_xx_00 : state <= 2'b00;
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7'b1_00_xx_00 : state <= 2'b00;
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7'b1_01_1x_00 : state <= 2'b10; // Start of DCACHE Kohaerenz
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7'b1_01_1x_00 : state <= 2'b10; // Start of DCACHE Kohaerenz
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7'b1_1x_1x_00 : state <= 2'b11; // Start of DMA
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7'b1_1x_1x_00 : state <= 2'b11; // Start of DMA
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//
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//
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7'b1_xx_x0_10 : state <= 2'b10; // without "ende" it stays as is
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7'b1_xx_x0_10 : state <= 2'b10; // without "ende" it stays as is
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7'b1_0x_x1_10 : state <= 2'b00; // DMA is not active
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7'b1_0x_x1_10 : state <= 2'b00; // DMA is not active
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7'b1_1x_x1_10 : state <= 2'b11; // to DMA !
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7'b1_1x_x1_10 : state <= 2'b11; // to DMA !
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//
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//
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7'b1_00_xx_11 : state <= 2'b00;
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7'b1_00_xx_11 : state <= 2'b00;
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7'b1_01_xx_11 : state <= 2'b10;
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7'b1_01_xx_11 : state <= 2'b10;
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7'b1_1x_xx_11 : state <= 2'b11;
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7'b1_1x_xx_11 : state <= 2'b11;
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default : state <= 2'b00;
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default : state <= 2'b00;
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endcase
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endcase
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assign STOP_ICRD = state[1]; // used for Multiplexer
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assign STOP_ICRD = state[1]; // used for Multiplexer
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assign dma_mode = state[0]; // internal Multiplexer
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assign dma_mode = state[0]; // internal Multiplexer
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assign STOP_CINV = state[1] & ~ENA_HK; // stops CINV if DMA access or Kohaerenz access
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assign STOP_CINV = state[1] & ~ENA_HK; // stops CINV if DMA access or Kohaerenz access
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assign ende = (counter[1:0] == 2'b00) & do_kill;
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assign ende = (counter[1:0] == 2'b00) & do_kill;
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assign ic_dma = STOP_ICRD & dma_mode; // Signal to DCACHE that ICACHE has stoped
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assign ic_dma = STOP_ICRD & dma_mode; // Signal to DCACHE that ICACHE has stoped
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always @(posedge BCLK) pipe <= STOP_ICRD;
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always @(posedge BCLK) pipe <= STOP_ICRD;
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assign RUN_ICRD = ~(STOP_ICRD | pipe); // Release for IC_READ
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assign RUN_ICRD = ~(STOP_ICRD | pipe); // Release for IC_READ
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always @(posedge BCLK) do_kill <= STOP_ICRD & ~dma_mode & ~do_kill; // Write pulse in Cache Valid RAM, 1 cycle on, 1 cycle off
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always @(posedge BCLK) do_kill <= STOP_ICRD & ~dma_mode & ~do_kill; // Write pulse in Cache Valid RAM, 1 cycle on, 1 cycle off
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assign KILL = do_kill | (KDET & dma_kolli);
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assign KILL = do_kill | (KDET & dma_kolli);
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// Valid Daten prepare : different sources for DMA and DCACHE Kohaerenz
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// Valid Daten prepare : different sources for DMA and DCACHE Kohaerenz
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assign cdaten = dma_mode ? C_VALID : CVALID;
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assign cdaten = dma_mode ? C_VALID : CVALID;
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assign kaddr = dma_mode ? {addr_r[11:4],found_1} : fifo_q;
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assign kaddr = dma_mode ? {addr_r[11:4],found_1} : fifo_q;
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assign KILLADR = kaddr[8:4];
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assign KILLADR = kaddr[8:4];
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always @(kaddr)
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always @(kaddr)
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case (kaddr[3:1])
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case (kaddr[3:1])
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3'h0 : clear = 8'hFE;
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3'h0 : clear = 8'hFE;
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3'h1 : clear = 8'hFD;
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3'h1 : clear = 8'hFD;
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3'h2 : clear = 8'hFB;
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3'h2 : clear = 8'hFB;
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3'h3 : clear = 8'hF7;
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3'h3 : clear = 8'hF7;
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3'h4 : clear = 8'hEF;
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3'h4 : clear = 8'hEF;
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3'h5 : clear = 8'hDF;
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3'h5 : clear = 8'hDF;
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3'h6 : clear = 8'hBF;
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3'h6 : clear = 8'hBF;
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3'h7 : clear = 8'h7F;
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3'h7 : clear = 8'h7F;
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endcase
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endcase
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assign new_0 = kaddr[0] ? cdaten[7:0] : (cdaten[7:0] & clear);
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assign new_0 = kaddr[0] ? cdaten[7:0] : (cdaten[7:0] & clear);
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assign new_1 = kaddr[0] ? (cdaten[15:8] & clear) : cdaten[15:8];
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assign new_1 = kaddr[0] ? (cdaten[15:8] & clear) : cdaten[15:8];
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assign NEWCVAL = {cdaten[23:16],new_1,new_0};
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assign NEWCVAL = {cdaten[23:16],new_1,new_0};
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// multiple signals are needed in DCACHE :
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// multiple signals are needed in DCACHE :
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assign ICTODC = {dma,ic_dma,~(counter[2:1] == 2'b11)};
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assign ICTODC = {dma,ic_dma,~(counter[2:1] == 2'b11)};
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endmodule
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 2. ICACHE_SM Instruction Cache State Machine
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// 2. DMUX Data Multiplexor
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module DMUX ( DRAM_Q, ADDR, CAP_Q );
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input [127:0] DRAM_Q;
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input [3:2] ADDR;
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output reg [31:0] CAP_Q;
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always @(ADDR or DRAM_Q)
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case (ADDR)
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2'b00 : CAP_Q = DRAM_Q[31:0];
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2'b01 : CAP_Q = DRAM_Q[63:32];
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2'b10 : CAP_Q = DRAM_Q[95:64];
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2'b11 : CAP_Q = DRAM_Q[127:96];
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endcase
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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// 3. ICACHE_SM Instruction Cache State Machine
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module ICACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, PTE_ACC,
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module ICACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, PTE_ACC,
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USE_CA, PTB_WR, PTB_SEL, USER, PROT_ERROR,
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USE_CA, PTB_WR, PTB_SEL, USER, PROT_ERROR,
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DRAM_ACC, IO_RD, IO_ACC, IC_PREQ, ACC_OK, HIT_ALL, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE );
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DRAM_ACC, IO_RD, IO_ACC, IC_PREQ, ACC_OK, HIT_ALL, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE );
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input BCLK;
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input BCLK;
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input BRESET;
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input BRESET;
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input IO_SPACE;
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input IO_SPACE;
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input MDONE; // Memory Done : Feedback from DRAM Controller, BCLK aligned
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input MDONE; // Memory Done : Feedback from DRAM Controller, BCLK aligned
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input IO_READY;
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input IO_READY;
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input MMU_HIT,CA_HIT;
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input MMU_HIT,CA_HIT;
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input READ;
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input READ;
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input PTE_ACC;
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input PTE_ACC;
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input USE_CA;
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input USE_CA;
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input PTB_WR,PTB_SEL;
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input PTB_WR,PTB_SEL;
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input USER;
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input USER;
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input PROT_ERROR;
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input PROT_ERROR;
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output reg DRAM_ACC,IO_RD;
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output reg DRAM_ACC,IO_RD;
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output IO_ACC;
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output IO_ACC;
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output IC_PREQ;
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output IC_PREQ;
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output ACC_OK;
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output ACC_OK;
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output HIT_ALL;
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output HIT_ALL;
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output CUPDATE;
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output CUPDATE;
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output AUX_DAT;
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output AUX_DAT;
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output reg NEW_PTB,PTB_ONE;
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output reg NEW_PTB,PTB_ONE;
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reg [3:0] new_state;
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reg [3:0] new_state;
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reg rd_done;
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reg rd_done;
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reg card_flag;
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reg card_flag;
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reg rd_rdy;
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reg rd_rdy;
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wire io_busy;
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wire io_busy;
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wire dram_go;
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wire dram_go;
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wire rd_ende;
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wire rd_ende;
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wire do_ca_rd;
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wire do_ca_rd;
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// Cycle : /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_
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// Cycle : /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_
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// Access : _/-----------------------------------\__
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// Access : _/-----------------------------------\__
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// State Machine : ____/----------------------------\______
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// State Machine : ____/----------------------------\______
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// Busy status ...
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// Busy status ...
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assign rd_ende = CA_HIT | rd_rdy; // CA_HIT only if Cache activ !
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assign rd_ende = CA_HIT | rd_rdy; // CA_HIT only if Cache activ !
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always @( READ // only READ , global control
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always @( READ // only READ , global control
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or PROT_ERROR // is not allowed !
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or PROT_ERROR // is not allowed !
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//
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//
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or IO_SPACE // indicates access in the IO_WELT
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or IO_SPACE // indicates access in the IO_WELT
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or io_busy // is already active ?
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or io_busy // is already active ?
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//
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//
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or MMU_HIT // Hit in the MMU , now only a READ can be active
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or MMU_HIT // Hit in the MMU , now only a READ can be active
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or rd_ende // Cache Hit
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or rd_ende // Cache Hit
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or DRAM_ACC // DRAM Access running
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or DRAM_ACC // DRAM Access running
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//
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//
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or PTE_ACC ) // PTE Access running
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or PTE_ACC ) // PTE Access running
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// #_# #_# #_#
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// #_# #_# #_#
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casex ({READ,PROT_ERROR,IO_SPACE,io_busy,MMU_HIT,rd_ende,DRAM_ACC,PTE_ACC})
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casex ({READ,PROT_ERROR,IO_SPACE,io_busy,MMU_HIT,rd_ende,DRAM_ACC,PTE_ACC})
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// MMU Miss : PTE load from memory
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// MMU Miss : PTE load from memory
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8'b10_xx_0xx_0 : new_state = 4'b0100; // start PTE access
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8'b10_xx_0xx_0 : new_state = 4'b0100; // start PTE access
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// IO-Address selected : external access starts if not already BUSY
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// IO-Address selected : external access starts if not already BUSY
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8'b10_10_1xx_x : new_state = 4'b0001;
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8'b10_10_1xx_x : new_state = 4'b0001;
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// DRAM Access : Cache Miss at READ
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// DRAM Access : Cache Miss at READ
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8'b10_0x_100_x : new_state = 4'b1010; // can start directly
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8'b10_0x_100_x : new_state = 4'b1010; // can start directly
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default : new_state = 4'b0;
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default : new_state = 4'b0;
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endcase
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endcase
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assign IO_ACC = new_state[0]; // to load the Register for Data and Addr
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assign IO_ACC = new_state[0]; // to load the Register for Data and Addr
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assign dram_go = new_state[1];
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assign dram_go = new_state[1];
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assign IC_PREQ = new_state[2]; // MMU to DCACHE !
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assign IC_PREQ = new_state[2]; // MMU to DCACHE !
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assign do_ca_rd = new_state[3];
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assign do_ca_rd = new_state[3];
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assign HIT_ALL = MMU_HIT & CA_HIT; // for Update "Last-Set" , MMU_HIT contains ZUGRIFF
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assign HIT_ALL = MMU_HIT & CA_HIT; // for Update "Last-Set" , MMU_HIT contains ZUGRIFF
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) card_flag <= 1'b0;
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if (!BRESET) card_flag <= 1'b0;
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else card_flag <= (do_ca_rd & ~rd_rdy) | (card_flag & ~MDONE);
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else card_flag <= (do_ca_rd & ~rd_rdy) | (card_flag & ~MDONE);
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assign CUPDATE = card_flag & USE_CA & MDONE; // USE_CA = ~CI & ~LDC;
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assign CUPDATE = card_flag & USE_CA & MDONE; // USE_CA = ~CI & ~LDC;
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always @(posedge BCLK) rd_rdy <= card_flag & MDONE;
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always @(posedge BCLK) rd_rdy <= card_flag & MDONE;
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// The cache RAM can not provide fast enough the data after an Update. In this case a secondary data path is activated
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// The cache RAM can not provide fast enough the data after an Update. In this case a secondary data path is activated
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assign AUX_DAT = rd_rdy;
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assign AUX_DAT = rd_rdy;
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// DRAM Interface :
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// DRAM Interface :
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always @(posedge BCLK) if (dram_go) DRAM_ACC <= 1'b1;
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always @(posedge BCLK) if (dram_go) DRAM_ACC <= 1'b1;
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else
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else
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DRAM_ACC <= DRAM_ACC & ~MDONE & BRESET;
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DRAM_ACC <= DRAM_ACC & ~MDONE & BRESET;
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// IO Interface :
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// IO Interface :
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always @(posedge BCLK)
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always @(posedge BCLK)
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begin
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begin
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if (IO_ACC) IO_RD <= READ; else IO_RD <= IO_RD & ~IO_READY & BRESET;
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if (IO_ACC) IO_RD <= READ; else IO_RD <= IO_RD & ~IO_READY & BRESET;
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end
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end
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assign io_busy = IO_RD | rd_done; // access is gone in next clock cycle, therefore blocked with "rd_done"
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assign io_busy = IO_RD | rd_done; // access is gone in next clock cycle, therefore blocked with "rd_done"
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always @(posedge BCLK) rd_done <= READ & IO_READY; // For READ one clock later for data to come through
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always @(posedge BCLK) rd_done <= READ & IO_READY; // For READ one clock later for data to come through
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// global feedback to opcode fetch unit : you can continue
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// global feedback to opcode fetch unit : you can continue
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assign ACC_OK = IO_SPACE ? rd_done : (READ & MMU_HIT & rd_ende);
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assign ACC_OK = IO_SPACE ? rd_done : (READ & MMU_HIT & rd_ende);
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// PTB1 und PTB0
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// PTB1 und PTB0
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always @(posedge BCLK) NEW_PTB <= PTB_WR; // to MMU Update Block
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always @(posedge BCLK) NEW_PTB <= PTB_WR; // to MMU Update Block
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always @(posedge BCLK) if (PTB_WR) PTB_ONE <= PTB_SEL;
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always @(posedge BCLK) if (PTB_WR) PTB_ONE <= PTB_SEL;
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endmodule
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endmodule
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