// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: STEUERUNG.v
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// Filename: STEUERUNG.v
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// Version: 2.0
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// Version: 3.0
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// History: 1.0 first release of 30 Mai 2015
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// Date: 2 December 2018
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// Date: 14 August 2016
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//
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//
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// Copyright (C) 2016 Udo Moeller
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// Copyright (C) 2018 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// STEUERUNG The control logic of M32632
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// STEUERUNG The control logic of M32632
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module STEUERUNG( BCLK, BRESET, DC_ACC_DONE, ACB_ZERO, DONE, INT_N, NMI_N, DC_ABORT, IC_INIT, DC_INIT, SAVE_PC, CFG,
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module STEUERUNG( BCLK, BRESET, DC_ACC_DONE, ACB_ZERO, DONE, INT_N, NMI_N, DC_ABORT, IC_INIT, DC_INIT, SAVE_PC, CFG,
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IACC_STAT, PROT_ERROR, IC_DIN, PC_NEW, PSR, STRING, TRAPS, IC_READ, DATA_HOLD, LD_DIN, LD_IMME,
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IACC_STAT, PROT_ERROR, IC_DIN, PC_NEW, PSR, STRING, TRAPS, IC_READ, DATA_HOLD, LD_DIN, LD_IMME,
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WREN, WR_REG, GENSTAT, ILO, COP_OP, IC_USER, ACC_FELD, DISP, IC_TEX, IMME_Q, INFO_AU, LD_OUT,
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WREN, WR_REG, GENSTAT, ILO, COP_OP, IC_USER, ACC_FELD, DISP, IC_TEX, IMME_Q, INFO_AU, LD_OUT,
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DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE, WRADR, RWVAL, Y_INIT,
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DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE, WRADR, RWVAL, Y_INIT,
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ENA_HK, STOP_CINV );
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ENA_HK, STOP_CINV );
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input BCLK;
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input BCLK;
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input BRESET;
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input BRESET;
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input DC_ACC_DONE;
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input DC_ACC_DONE;
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input ACB_ZERO;
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input ACB_ZERO;
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input DONE;
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input DONE;
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input INT_N;
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input INT_N;
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input NMI_N;
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input NMI_N;
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input DC_ABORT;
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input DC_ABORT;
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input IC_INIT;
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input IC_INIT;
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input DC_INIT;
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input DC_INIT;
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input SAVE_PC;
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input SAVE_PC;
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input Y_INIT;
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input Y_INIT;
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input [8:0] CFG;
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input [8:0] CFG;
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input [3:0] IACC_STAT;
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input [3:0] IACC_STAT;
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input PROT_ERROR;
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input PROT_ERROR;
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input [31:0] IC_DIN;
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input [31:0] IC_DIN;
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input [31:0] PC_NEW;
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input [31:0] PC_NEW;
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input [11:0] PSR;
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input [11:0] PSR;
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input [4:0] STRING;
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input [4:0] STRING;
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input [5:0] TRAPS;
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input [5:0] TRAPS;
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input STOP_CINV;
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input STOP_CINV;
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output IC_READ;
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output IC_READ;
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output DATA_HOLD;
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output DATA_HOLD;
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output LD_DIN;
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output LD_DIN;
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output LD_IMME;
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output LD_IMME;
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output WREN;
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output WREN;
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output WR_REG;
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output WR_REG;
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output [2:0] GENSTAT;
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output [2:0] GENSTAT;
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output IC_USER;
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output IC_USER;
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output [14:0] ACC_FELD;
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output [14:0] ACC_FELD;
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output [31:0] DISP;
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output [31:0] DISP;
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output [2:0] IC_TEX;
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output [2:0] IC_TEX;
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output [31:0] IMME_Q;
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output [31:0] IMME_Q;
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output [6:0] INFO_AU;
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output [6:0] INFO_AU;
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output [1:0] LD_OUT;
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output [1:0] LD_OUT;
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output [12:0] DETOIP;
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output [12:0] DETOIP;
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output [1:0] MMU_UPDATE;
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output [1:0] MMU_UPDATE;
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output [10:0] OPER;
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output [10:0] OPER;
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output [31:0] PC_ARCHI;
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output [31:0] PC_ARCHI;
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output [31:0] PC_ICACHE;
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output [31:0] PC_ICACHE;
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output [7:0] RDAA;
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output [7:0] RDAA;
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output [7:0] RDAB;
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output [7:0] RDAB;
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output [1:0] START;
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output [1:0] START;
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output [1:0] WMASKE;
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output [1:0] WMASKE;
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output [5:0] WRADR;
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output [5:0] WRADR;
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output [2:0] RWVAL;
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output [2:0] RWVAL;
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output ENA_HK;
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output ENA_HK;
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output ILO;
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output ILO;
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output [23:0] COP_OP;
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output [23:0] COP_OP;
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wire [55:0] OPREG;
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wire [55:0] OPREG;
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wire IC_ABORT;
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wire IC_ABORT;
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wire INIT_DONE;
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wire INIT_DONE;
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wire UNDEF;
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wire UNDEF;
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wire ILLEGAL;
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wire ILLEGAL;
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wire [2:0] ANZ_VAL;
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wire [2:0] ANZ_VAL;
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wire [31:0] PC_SAVE;
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wire [31:0] PC_SAVE;
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wire NEW;
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wire NEW;
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wire RESTART;
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wire RESTART;
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wire STOP_IC;
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wire STOP_IC;
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wire [1:0] ALSB;
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wire [1:0] ALSB;
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wire [2:0] USED;
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wire [2:0] USED;
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wire NEXT_ADR;
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wire NEXT_ADR;
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wire NEW_PC;
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wire NEW_PC;
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wire NEXT_PCA;
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wire NEXT_PCA;
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wire LOAD_PC;
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wire LOAD_PC;
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wire [31:0] DISP_BR;
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wire [31:0] DISP_BR;
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DECODER BEFEHLS_DEC(
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DECODER BEFEHLS_DEC(
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.BCLK(BCLK),
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.BCLK(BCLK),
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.BRESET(BRESET),
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.BRESET(BRESET),
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.ACC_DONE(DC_ACC_DONE),
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.ACC_DONE(DC_ACC_DONE),
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.ACB_ZERO(ACB_ZERO),
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.ACB_ZERO(ACB_ZERO),
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.DONE(DONE),
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.DONE(DONE),
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.NMI_N(NMI_N),
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.NMI_N(NMI_N),
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.INT_N(INT_N),
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.INT_N(INT_N),
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.DC_ABORT(DC_ABORT),
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.DC_ABORT(DC_ABORT),
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.IC_ABORT(IC_ABORT),
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.IC_ABORT(IC_ABORT),
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.INIT_DONE(INIT_DONE),
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.INIT_DONE(INIT_DONE),
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.UNDEF(UNDEF),
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.UNDEF(UNDEF),
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.ILL(ILLEGAL),
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.ILL(ILLEGAL),
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.IC_READ(IC_READ),
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.IC_READ(IC_READ),
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.ANZ_VAL(ANZ_VAL),
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.ANZ_VAL(ANZ_VAL),
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.CFG(CFG),
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.CFG(CFG),
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.OPREG(OPREG),
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.OPREG(OPREG),
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.PC_SAVE(PC_SAVE),
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.PC_SAVE(PC_SAVE),
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.PSR(PSR),
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.PSR(PSR),
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.STRING(STRING),
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.STRING(STRING),
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.TRAPS(TRAPS),
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.TRAPS(TRAPS),
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.NEW(NEW),
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.NEW(NEW),
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.WREN(WREN),
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.WREN(WREN),
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.LD_DIN(LD_DIN),
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.LD_DIN(LD_DIN),
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.LD_IMME(LD_IMME),
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.LD_IMME(LD_IMME),
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.NEXT_PCA(NEXT_PCA),
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.NEXT_PCA(NEXT_PCA),
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.WR_REG(WR_REG),
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.WR_REG(WR_REG),
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.LOAD_PC(LOAD_PC),
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.LOAD_PC(LOAD_PC),
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.GENSTAT(GENSTAT),
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.GENSTAT(GENSTAT),
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.RESTART(RESTART),
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.RESTART(RESTART),
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.STOP_IC(STOP_IC),
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.STOP_IC(STOP_IC),
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.ACC_FELD(ACC_FELD),
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.ACC_FELD(ACC_FELD),
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.DISP(DISP),
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.DISP(DISP),
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.DISP_BR(DISP_BR),
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.DISP_BR(DISP_BR),
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.IMME_Q(IMME_Q),
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.IMME_Q(IMME_Q),
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.INFO_AU(INFO_AU),
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.INFO_AU(INFO_AU),
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.LD_OUT(LD_OUT),
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.LD_OUT(LD_OUT),
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.DETOIP(DETOIP),
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.DETOIP(DETOIP),
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.MMU_UPDATE(MMU_UPDATE),
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.MMU_UPDATE(MMU_UPDATE),
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.OPER(OPER),
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.OPER(OPER),
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.RDAA(RDAA),
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.RDAA(RDAA),
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.RDAB(RDAB),
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.RDAB(RDAB),
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.START(START),
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.START(START),
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.USED(USED),
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.USED(USED),
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.WMASKE(WMASKE),
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.WMASKE(WMASKE),
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.WRADR(WRADR),
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.WRADR(WRADR),
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.RWVAL(RWVAL),
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.RWVAL(RWVAL),
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.ENA_HK(ENA_HK),
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.ENA_HK(ENA_HK),
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.ILO(ILO),
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.ILO(ILO),
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.COP_OP(COP_OP),
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.COP_OP(COP_OP),
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.STOP_CINV(STOP_CINV),
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.STOP_CINV(STOP_CINV),
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.PHOUT());
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.PHOUT());
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ILL_UNDEF CHECKER(
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ILL_UNDEF CHECKER(
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.USER(PSR[8]),
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.USER(PSR[8]),
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.ANZ_VAL(ANZ_VAL),
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.ANZ_VAL(ANZ_VAL),
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.CFG(CFG[3:1]),
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.CFG(CFG[3:1]),
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.OPREG(OPREG[23:0]),
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.OPREG(OPREG[23:0]),
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.ILL(ILLEGAL),
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.ILL(ILLEGAL),
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.UNDEF(UNDEF));
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.UNDEF(UNDEF));
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OPDEC_REG OPC_REG(
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OPDEC_REG OPC_REG(
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.BCLK(BCLK),
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.BCLK(BCLK),
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.BRESET(BRESET),
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.BRESET(BRESET),
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.NEW(NEW),
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.NEW(NEW),
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.DC_INIT(DC_INIT),
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.DC_INIT(DC_INIT),
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.IC_INIT(IC_INIT),
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.IC_INIT(IC_INIT),
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.Y_INIT(Y_INIT),
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.Y_INIT(Y_INIT),
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.RESTART(RESTART),
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.RESTART(RESTART),
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.STOP_IC(STOP_IC),
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.STOP_IC(STOP_IC),
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.ACC_STAT(IACC_STAT),
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.ACC_STAT(IACC_STAT),
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.PROT_ERROR(PROT_ERROR),
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.PROT_ERROR(PROT_ERROR),
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.ALSB(ALSB),
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.ALSB(ALSB),
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.IC_DIN(IC_DIN),
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.IC_DIN(IC_DIN),
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.USED(USED),
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.USED(USED),
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.IC_READ(IC_READ),
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.IC_READ(IC_READ),
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.NEXT_ADR(NEXT_ADR),
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.NEXT_ADR(NEXT_ADR),
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.DATA_HOLD(DATA_HOLD),
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.DATA_HOLD(DATA_HOLD),
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.NEW_PC(NEW_PC),
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.NEW_PC(NEW_PC),
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.ABORT(IC_ABORT),
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.ABORT(IC_ABORT),
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.INIT_DONE(INIT_DONE),
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.INIT_DONE(INIT_DONE),
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.ANZ_VAL(ANZ_VAL),
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.ANZ_VAL(ANZ_VAL),
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.IC_TEX(IC_TEX),
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.IC_TEX(IC_TEX),
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.OPREG(OPREG));
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.OPREG(OPREG));
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PROG_COUNTER PCS(
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PROG_COUNTER PCS(
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.BCLK(BCLK),
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.BCLK(BCLK),
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.BRESET(BRESET),
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.BRESET(BRESET),
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.NEXT_ADR(NEXT_ADR),
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.NEXT_ADR(NEXT_ADR),
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.NEW_PC(NEW_PC),
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.NEW_PC(NEW_PC),
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.NEXT_PCA(NEXT_PCA),
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.NEXT_PCA(NEXT_PCA),
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.NEW(NEW),
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.NEW(NEW),
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.LOAD_PC(LOAD_PC),
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.LOAD_PC(LOAD_PC),
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.USER(PSR[8]),
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.USER(PSR[8]),
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.SAVE_PC(SAVE_PC),
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.SAVE_PC(SAVE_PC),
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.FPU_TRAP(TRAPS[0]),
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.FPU_TRAP(TRAPS[0]),
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.ADIVAR(INFO_AU[3]),
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.ADIVAR(INFO_AU[3]),
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.DISP(DISP_BR),
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.DISP(DISP_BR),
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.PC_NEW(PC_NEW),
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.PC_NEW(PC_NEW),
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.USED(USED),
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.USED(USED),
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.IC_USER(IC_USER),
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.IC_USER(IC_USER),
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.ALSB(ALSB),
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.ALSB(ALSB),
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.PC_ARCHI(PC_ARCHI),
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.PC_ARCHI(PC_ARCHI),
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.PC_ICACHE(PC_ICACHE),
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.PC_ICACHE(PC_ICACHE),
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.PC_SAVE(PC_SAVE));
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.PC_SAVE(PC_SAVE));
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endmodule
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endmodule
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