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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//

// This file is part of the M32632 project

// This file is part of the M32632 project

// http://opencores.org/project,m32632

// http://opencores.org/project,m32632

//

//

// Filename: STEUER_MISC.v

// Filename: STEUER_MISC.v

//

//

// 

// 

// This source file may be used and distributed without 

// This source file may be used and distributed without 

// restriction provided that this copyright statement is not 

// restriction provided that this copyright statement is not 

// removed from the file and that any derivative work contains 

// removed from the file and that any derivative work contains 

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// the original copyright notice and the associated disclaimer.

// 

// 

// This source file is free software; you can redistribute it 

// This source file is free software; you can redistribute it 

// and/or modify it under the terms of the GNU Lesser General 

// and/or modify it under the terms of the GNU Lesser General 

// Public License as published by the Free Software Foundation;

// Public License as published by the Free Software Foundation;

// either version 2.1 of the License, or (at your option) any 

// either version 2.1 of the License, or (at your option) any 

// later version. 

// later version. 

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// 

// This source is distributed in the hope that it will be 

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// PURPOSE. See the GNU Lesser General Public License for more 

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// details. 

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// 

// You should have received a copy of the GNU Lesser General 

// You should have received a copy of the GNU Lesser General 

// Public License along with this source; if not, download it 

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// from http://www.opencores.org/lgpl.shtml 

// from http://www.opencores.org/lgpl.shtml 

// 

// 

// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//

//      Modules contained in this file:

//      Modules contained in this file:

//      1. OPDEC_REG    Central Instruction Register

//      1. OPDEC_REG    Central Instruction Register

//      2. PROG_COUNTER Program Counters

//      2. PROG_COUNTER Program Counters

//      3. REG_LIST             Register List Evaluation

//      3. REG_LIST             Register List Evaluation

//      4. ILL_UNDEF    Illegal and Undefined Opcodes Detection

//      4. ILL_UNDEF    Illegal and Undefined Opcodes Detection

//      5. GRUPPE_2             Decoder and State Machine for GRUPPE_2 Opcodes

//      5. GRUPPE_2             Decoder and State Machine for GRUPPE_2 Opcodes

//

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//

//      1. OPDEC_REG    Central Instruction Register

//      1. OPDEC_REG    Central Instruction Register

//

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module OPDEC_REG ( BCLK, BRESET, NEW, ACC_STAT, PROT_ERROR, ALSB, USED, IC_DIN, IC_INIT, DC_INIT, Y_INIT, RESTART, STOP_IC,

module OPDEC_REG ( BCLK, BRESET, NEW, ACC_STAT, PROT_ERROR, ALSB, USED, IC_DIN, IC_INIT, DC_INIT, Y_INIT, RESTART, STOP_IC,

                                   OPREG, ANZ_VAL, IC_READ, NEW_PC, NEXT_ADR, DATA_HOLD, ABORT, IC_TEX, INIT_DONE);

                                   OPREG, ANZ_VAL, IC_READ, NEW_PC, NEXT_ADR, DATA_HOLD, ABORT, IC_TEX, INIT_DONE);

        input                   BCLK,BRESET;

        input                   BCLK,BRESET;

        input                   NEW;            // a program jump took place

        input                   NEW;            // a program jump took place

        input    [3:0]   ACC_STAT;       // ICACHE signals data is available or Abort

        input    [3:0]   ACC_STAT;       // ICACHE signals data is available or Abort

        input                   PROT_ERROR;     // comes direct from ICACHE

        input                   PROT_ERROR;     // comes direct from ICACHE

        input    [1:0]   ALSB;           // lower addressbits of access address to ICACHE

        input    [1:0]   ALSB;           // lower addressbits of access address to ICACHE

        input    [2:0]   USED;           // Message from DECODER how many bytes were used

        input    [2:0]   USED;           // Message from DECODER how many bytes were used

        input   [31:0]   IC_DIN;         // ICACHE Data

        input   [31:0]   IC_DIN;         // ICACHE Data

        input                   IC_INIT,DC_INIT,Y_INIT; // Initialising or new setting is running

        input                   IC_INIT,DC_INIT,Y_INIT; // Initialising or new setting is running

        input                   RESTART;        // "Break" of Instruction Pipeline - set up new i.e. after load of PSR

        input                   RESTART;        // "Break" of Instruction Pipeline - set up new i.e. after load of PSR

        input                   STOP_IC;        // For LMR and CINV

        input                   STOP_IC;        // For LMR and CINV

        output  [55:0]   OPREG;          // this is the Central Opcode Decode Register, length = 7 bytes

        output  [55:0]   OPREG;          // this is the Central Opcode Decode Register, length = 7 bytes

        output   [2:0]   ANZ_VAL;

        output   [2:0]   ANZ_VAL;

        output                  IC_READ;

        output                  IC_READ;

        output                  NEW_PC;

        output                  NEW_PC;

        output                  NEXT_ADR;

        output                  NEXT_ADR;

        output                  DATA_HOLD;

        output                  DATA_HOLD;

        output                  ABORT;

        output                  ABORT;

        output   [2:0]   IC_TEX;

        output   [2:0]   IC_TEX;

        output                  INIT_DONE;

        output                  INIT_DONE;

        reg             [55:0]   OPREG;

        reg             [55:0]   OPREG;

        reg              [2:0]   ANZ_VAL;

        reg              [2:0]   ANZ_VAL;

        reg                             IC_READ;

        reg                             IC_READ;

        reg                             ABORT;

        reg                             ABORT;

        reg                             abort_flag;

        reg                             abort_flag;

        reg              [2:0]   IC_TEX;

        reg              [2:0]   IC_TEX;

        reg             [55:0]   data_to_ri;

        reg             [55:0]   data_to_ri;

        reg                             old_init;

        reg                             old_init;

        reg                             pre_new;

        reg                             pre_new;

        reg                             new_reg;

        reg                             new_reg;

        reg                             nseq_flag;

        reg                             nseq_flag;

        reg                             stop_init;

        reg                             stop_init;

        wire     [2:0]   new_anz;

        wire     [2:0]   new_anz;

        wire                    new_restart;

        wire                    new_restart;

        wire                    acc_err,acc_ok,acc_ende;

        wire                    acc_err,acc_ok,acc_ende;

        // ++++++++++++++++++++  Evaluation of ACC_STAT from Instructioncache  ++++++++++++++++++++++++++++

        // ++++++++++++++++++++  Evaluation of ACC_STAT from Instructioncache  ++++++++++++++++++++++++++++

        // ACC_STAT[3:0] : PROT_ERROR , ABO_LEVEL1 , ABORT , ACC_OK

        // ACC_STAT[3:0] : PROT_ERROR , ABO_LEVEL1 , ABORT , ACC_OK

        assign acc_err = ACC_STAT[3] | ACC_STAT[1] | PROT_ERROR;

        assign acc_err = ACC_STAT[3] | ACC_STAT[1] | PROT_ERROR;

        assign acc_ok  = ACC_STAT[0];

        assign acc_ok  = ACC_STAT[0];

        always @(posedge BCLK or negedge BRESET)        // is kept until DECODER really needs the data !

        always @(posedge BCLK or negedge BRESET)        // is kept until DECODER really needs the data !

                if (!BRESET) ABORT <= 1'b0;

                if (!BRESET) ABORT <= 1'b0;

                  else ABORT <=  (acc_err & ~(new_restart | pre_new)) | (ABORT & ~NEW_PC);

                  else ABORT <=  (acc_err & ~(new_restart | pre_new)) | (ABORT & ~NEW_PC);

        always @(posedge BCLK) if (acc_err) IC_TEX <= (ACC_STAT[3] | PROT_ERROR) ? {nseq_flag,2'b11} : {nseq_flag,~ACC_STAT[2],ACC_STAT[2]};

        always @(posedge BCLK) if (acc_err) IC_TEX <= (ACC_STAT[3] | PROT_ERROR) ? {nseq_flag,2'b11} : {nseq_flag,~ACC_STAT[2],ACC_STAT[2]};

        always @(posedge BCLK) nseq_flag <= NEW_PC | (nseq_flag & ~acc_ok);     // for MMU Status Register

        always @(posedge BCLK) nseq_flag <= NEW_PC | (nseq_flag & ~acc_ok);     // for MMU Status Register

        always @(posedge BCLK) abort_flag <= acc_err;

        always @(posedge BCLK) abort_flag <= acc_err;

        assign acc_ende = ~IC_READ | acc_ok | abort_flag;       // abort_flag one cycle later is ok ! If no ICache access always end

        assign acc_ende = ~IC_READ | acc_ok | abort_flag;       // abort_flag one cycle later is ok ! If no ICache access always end

        assign new_restart = NEW | RESTART;     // They are pulses

        assign new_restart = NEW | RESTART;     // They are pulses

        // Branch work out : NEW/RESTART notice if access still not ended

        // Branch work out : NEW/RESTART notice if access still not ended

        always @(posedge BCLK) pre_new <= (new_restart & ~acc_ende) | (pre_new & ~acc_ende & BRESET);

        always @(posedge BCLK) pre_new <= (new_restart & ~acc_ende) | (pre_new & ~acc_ende & BRESET);

        assign NEW_PC = (new_restart | pre_new) & acc_ende;     // At the end of access geenerate new address !

        assign NEW_PC = (new_restart | pre_new) & acc_ende;     // At the end of access geenerate new address !

        // There are 2 "NEW/RESTART" : "new_restart" combinatorical out of DECODER, "pre_new" out of Register

        // There are 2 "NEW/RESTART" : "new_restart" combinatorical out of DECODER, "pre_new" out of Register

        always @(posedge BCLK) new_reg <= new_restart | pre_new | (new_reg & ~acc_ende & BRESET);

        always @(posedge BCLK) new_reg <= new_restart | pre_new | (new_reg & ~acc_ende & BRESET);

        always @(USED or OPREG) // Data first shift to the right

        always @(USED or OPREG) // Data first shift to the right

                case (USED)

                case (USED)

                  3'b000 : data_to_ri = OPREG;

                  3'b000 : data_to_ri = OPREG;

                  3'b001 : data_to_ri =               { 8'hxx, OPREG[55:8]};

                  3'b001 : data_to_ri =               { 8'hxx, OPREG[55:8]};

                  3'b010 : data_to_ri =             {16'hxxxx,OPREG[55:16]};

                  3'b010 : data_to_ri =             {16'hxxxx,OPREG[55:16]};

                  3'b011 : data_to_ri =          {24'hxx_xxxx,OPREG[55:24]};

                  3'b011 : data_to_ri =          {24'hxx_xxxx,OPREG[55:24]};

                  3'b100 : data_to_ri =        {32'hxxxx_xxxx,OPREG[55:32]};

                  3'b100 : data_to_ri =        {32'hxxxx_xxxx,OPREG[55:32]};

                  3'b101 : data_to_ri =     {40'hxx_xxxx_xxxx,OPREG[55:40]};

                  3'b101 : data_to_ri =     {40'hxx_xxxx_xxxx,OPREG[55:40]};

                  3'b110 : data_to_ri =   {48'hxxxx_xxxx_xxxx,OPREG[55:48]};

                  3'b110 : data_to_ri =   {48'hxxxx_xxxx_xxxx,OPREG[55:48]};

                  3'b111 : data_to_ri = 56'hxx_xxxx_xxxx_xxxx;

                  3'b111 : data_to_ri = 56'hxx_xxxx_xxxx_xxxx;

                endcase

                endcase

        assign new_anz = ANZ_VAL - USED;

        assign new_anz = ANZ_VAL - USED;

        always @(posedge BCLK)

        always @(posedge BCLK)

                casex ({new_reg,acc_ok,ALSB,new_anz})

                casex ({new_reg,acc_ok,ALSB,new_anz})

                  7'b1_100_xxx : OPREG <=        {24'hxx_xxxx,IC_DIN};

                  7'b1_100_xxx : OPREG <=        {24'hxx_xxxx,IC_DIN};

                  7'b1_101_xxx : OPREG <=      {32'hxxxx_xxxx,IC_DIN[31:8]};

                  7'b1_101_xxx : OPREG <=      {32'hxxxx_xxxx,IC_DIN[31:8]};

                  7'b1_110_xxx : OPREG <=   {40'hxx_xxxx_xxxx,IC_DIN[31:16]};

                  7'b1_110_xxx : OPREG <=   {40'hxx_xxxx_xxxx,IC_DIN[31:16]};

                  7'b1_111_xxx : OPREG <= {48'hxxxx_xxxx_xxxx,IC_DIN[31:24]};

                  7'b1_111_xxx : OPREG <= {48'hxxxx_xxxx_xxxx,IC_DIN[31:24]};

                  7'b0_0xx_xxx : OPREG <= data_to_ri;

                  7'b0_0xx_xxx : OPREG <= data_to_ri;

                  7'b0_1xx_000 : OPREG <= {24'hxx_xxxx,IC_DIN};

                  7'b0_1xx_000 : OPREG <= {24'hxx_xxxx,IC_DIN};

                  7'b0_1xx_001 : OPREG <= {   16'hxxxx,IC_DIN, data_to_ri[7:0]};

                  7'b0_1xx_001 : OPREG <= {   16'hxxxx,IC_DIN, data_to_ri[7:0]};

                  7'b0_1xx_010 : OPREG <= {      8'hxx,IC_DIN,data_to_ri[15:0]};

                  7'b0_1xx_010 : OPREG <= {      8'hxx,IC_DIN,data_to_ri[15:0]};

                  7'b0_1xx_011 : OPREG <= {            IC_DIN,data_to_ri[23:0]};

                  7'b0_1xx_011 : OPREG <= {            IC_DIN,data_to_ri[23:0]};

                  7'b0_1xx_1xx : OPREG <= data_to_ri;

                  7'b0_1xx_1xx : OPREG <= data_to_ri;

                endcase

                endcase

        always @(posedge BCLK or negedge BRESET)

        always @(posedge BCLK or negedge BRESET)

                if (!BRESET) ANZ_VAL <= 3'b000;

                if (!BRESET) ANZ_VAL <= 3'b000;

                  else

                  else

                        casex ({new_restart,new_reg,acc_ok,new_anz[2]})

                        casex ({new_restart,new_reg,acc_ok,new_anz[2]})

                          4'b1x_x_x : ANZ_VAL <= 3'b000;        // hard setting to 0

                          4'b1x_x_x : ANZ_VAL <= 3'b000;        // hard setting to 0

                          4'b01_0_x : ANZ_VAL <= 3'b000;

                          4'b01_0_x : ANZ_VAL <= 3'b000;

                          4'b01_1_x : ANZ_VAL <= pre_new ? 3'b000 : 3'b100 - {1'b0,ALSB};

                          4'b01_1_x : ANZ_VAL <= pre_new ? 3'b000 : 3'b100 - {1'b0,ALSB};

                          4'b00_0_x : ANZ_VAL <= new_anz;

                          4'b00_0_x : ANZ_VAL <= new_anz;

                          4'b00_1_0 : ANZ_VAL <= new_anz + 3'b100;

                          4'b00_1_0 : ANZ_VAL <= new_anz + 3'b100;

                          4'b00_1_1 : ANZ_VAL <= new_anz;

                          4'b00_1_1 : ANZ_VAL <= new_anz;

                        endcase

                        endcase

        assign NEXT_ADR = new_reg ? (acc_ok & ~pre_new) : (acc_ok & ~new_anz[2]);       // switches MUX at PC resp. ICACHE

        assign NEXT_ADR = new_reg ? (acc_ok & ~pre_new) : (acc_ok & ~new_anz[2]);       // switches MUX at PC resp. ICACHE

        // Instruction CACHE Control : READ is coming after all INITs are done

        // Instruction CACHE Control : READ is coming after all INITs are done

        always @(posedge BCLK) old_init <= IC_INIT | DC_INIT | Y_INIT;

        always @(posedge BCLK) old_init <= IC_INIT | DC_INIT | Y_INIT;

        assign INIT_DONE = old_init & ~IC_INIT & ~DC_INIT;

        assign INIT_DONE = old_init & ~IC_INIT & ~DC_INIT;

        always @(posedge BCLK or negedge BRESET)

        always @(posedge BCLK or negedge BRESET)

                if (!BRESET) stop_init <= 1'b0;

                if (!BRESET) stop_init <= 1'b0;

                        else stop_init <= stop_init | IC_READ;

                        else stop_init <= stop_init | IC_READ;

        // The INIT_DONE should come after Reset. But it comes too at LMR PTB therefore extra enable after Reset !

        // The INIT_DONE should come after Reset. But it comes too at LMR PTB therefore extra enable after Reset !

        always @(posedge BCLK or negedge BRESET)

        always @(posedge BCLK or negedge BRESET)

                if (!BRESET) IC_READ <= 1'b0;

                if (!BRESET) IC_READ <= 1'b0;

                        else IC_READ <= (IC_READ & ~acc_err & ~(STOP_IC & acc_ok)) | NEW_PC | (INIT_DONE & ~stop_init);

                        else IC_READ <= (IC_READ & ~acc_err & ~(STOP_IC & acc_ok)) | NEW_PC | (INIT_DONE & ~stop_init);

        // The Opcode-Register can not store the data : keep them in ICACHE at IO-access

        // The Opcode-Register can not store the data : keep them in ICACHE at IO-access

        assign DATA_HOLD = ~new_restart & ~new_reg & acc_ok & new_anz[2];

        assign DATA_HOLD = ~new_restart & ~new_reg & acc_ok & new_anz[2];

endmodule

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//

//      2. PROG_COUNTER Program Counters

//      2. PROG_COUNTER Program Counters

//

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module PROG_COUNTER ( BCLK, BRESET, NEW, LOAD_PC, NEW_PC, NEXT_ADR, NEXT_PCA, DISP, PC_NEW, USED, USER, SAVE_PC, FPU_TRAP,

module PROG_COUNTER ( BCLK, BRESET, NEW, LOAD_PC, NEW_PC, NEXT_ADR, NEXT_PCA, DISP, PC_NEW, USED, USER, SAVE_PC, FPU_TRAP,

                                          ADIVAR, PC_ARCHI, PC_ICACHE, PC_SAVE, ALSB, IC_USER);

                                          ADIVAR, PC_ARCHI, PC_ICACHE, PC_SAVE, ALSB, IC_USER);

        input                   BCLK,BRESET;

        input                   BCLK,BRESET;

        input                   NEW;

        input                   NEW;

        input                   LOAD_PC;

        input                   LOAD_PC;

        input                   NEW_PC;

        input                   NEW_PC;

        input                   NEXT_ADR;

        input                   NEXT_ADR;

        input                   NEXT_PCA;

        input                   NEXT_PCA;

        input   [31:0]   DISP;

        input   [31:0]   DISP;

        input   [31:0]   PC_NEW;

        input   [31:0]   PC_NEW;

        input    [2:0]   USED;

        input    [2:0]   USED;

        input                   USER;

        input                   USER;

        input                   SAVE_PC;

        input                   SAVE_PC;

        input                   FPU_TRAP;

        input                   FPU_TRAP;

        input                   ADIVAR;

        input                   ADIVAR;

        output  [31:0]   PC_ARCHI;       // goes to Datapath

        output  [31:0]   PC_ARCHI;       // goes to Datapath

        output  [31:0]   PC_ICACHE;

        output  [31:0]   PC_ICACHE;

        output  [31:0]   PC_SAVE;        // is the return address

        output  [31:0]   PC_SAVE;        // is the return address

        output   [1:0]   ALSB;

        output   [1:0]   ALSB;

        output                  IC_USER;

        output                  IC_USER;

        reg             [31:0]   PC_ARCHI;

        reg             [31:0]   PC_ARCHI;

        reg             [31:0]   pc_adduse;

        reg             [31:0]   pc_adduse;

        reg             [31:0]   pc_ic_reg;

        reg             [31:0]   pc_ic_reg;

        reg             [31:0]   fpu_trap_pc;

        reg             [31:0]   fpu_trap_pc;

        reg                             IC_USER;

        reg                             IC_USER;

        wire    [31:0]   branch,pc_jump,next_pc,pc_icache_i;

        wire    [31:0]   branch,pc_jump,next_pc,pc_icache_i;

        assign PC_SAVE = pc_adduse + {29'h0,USED};

        assign PC_SAVE = pc_adduse + {29'h0,USED};

        assign branch  = PC_ARCHI + DISP;

        assign branch  = PC_ARCHI + DISP;

        assign pc_jump = LOAD_PC ? PC_NEW : branch;

        assign pc_jump = LOAD_PC ? PC_NEW : branch;

        assign next_pc = NEW ? pc_jump : PC_SAVE;       // Only at NEW is the DISP correct !

        assign next_pc = NEW ? pc_jump : PC_SAVE;       // Only at NEW is the DISP correct !

        always @(posedge BCLK or negedge BRESET)

        always @(posedge BCLK or negedge BRESET)

                if (!BRESET) pc_adduse <= 32'h0;

                if (!BRESET) pc_adduse <= 32'h0;

                  else

                  else

                        pc_adduse <= next_pc;

                        pc_adduse <= next_pc;

        // The Architectur - PC : Address mode "Programm Memory"-relativ

        // The Architectur - PC : Address mode "Programm Memory"-relativ

        // no BRESET because NEXT_PCA is immediately valid

        // no BRESET because NEXT_PCA is immediately valid

        always @(posedge BCLK)

        always @(posedge BCLK)

                if (FPU_TRAP) PC_ARCHI <= fpu_trap_pc;  // go back !

                if (FPU_TRAP) PC_ARCHI <= fpu_trap_pc;  // go back !

                  else

                  else

                        if (NEXT_PCA) PC_ARCHI <= pc_adduse;

                        if (NEXT_PCA) PC_ARCHI <= pc_adduse;

        always @(posedge BCLK) if (SAVE_PC) fpu_trap_pc <= PC_ARCHI;    // Special storage for PC for FPU Trap

        always @(posedge BCLK) if (SAVE_PC) fpu_trap_pc <= PC_ARCHI;    // Special storage for PC for FPU Trap

        always @(posedge BCLK or negedge BRESET)

        always @(posedge BCLK or negedge BRESET)

                if (!BRESET) pc_ic_reg <= 32'h0;

                if (!BRESET) pc_ic_reg <= 32'h0;

                  else

                  else

                        pc_ic_reg <= pc_icache_i;

                        pc_ic_reg <= pc_icache_i;

        // NEW is only one cycle long - but in pc_adduse is the PC stored when ACC_OK is not there and therefore NEW_PC

        // NEW is only one cycle long - but in pc_adduse is the PC stored when ACC_OK is not there and therefore NEW_PC

        // is used to initiate a new access in ICACHE

        // is used to initiate a new access in ICACHE

        assign pc_icache_i = NEW_PC ? (NEW ? pc_jump : pc_adduse) : (NEXT_ADR ? ({pc_ic_reg[31:2],2'b00} + 32'h0000_0004) : pc_ic_reg);

        assign pc_icache_i = NEW_PC ? (NEW ? pc_jump : pc_adduse) : (NEXT_ADR ? ({pc_ic_reg[31:2],2'b00} + 32'h0000_0004) : pc_ic_reg);

        // This MUX is extra for LMR IVAR,... and CINV build in

        // This MUX is extra for LMR IVAR,... and CINV build in

        assign PC_ICACHE = {(ADIVAR ? PC_NEW[31:4] : pc_icache_i[31:4]),pc_icache_i[3:0]};

        assign PC_ICACHE = {(ADIVAR ? PC_NEW[31:4] : pc_icache_i[31:4]),pc_icache_i[3:0]};

        assign ALSB = pc_ic_reg[1:0];    // for OPDEC_REG

        assign ALSB = pc_ic_reg[1:0];    // for OPDEC_REG

        // The IC_USER flag is allowed to switch synchronously with one cycle delay to PC_ICACHE

        // The IC_USER flag is allowed to switch synchronously with one cycle delay to PC_ICACHE

        always @(posedge BCLK or negedge BRESET)

        always @(posedge BCLK or negedge BRESET)

                if (!BRESET) IC_USER <= 1'b0;

                if (!BRESET) IC_USER <= 1'b0;

                  else

                  else

                        if (NEW_PC) IC_USER <= USER;

                        if (NEW_PC) IC_USER <= USER;

endmodule

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//

//      3. REG_LIST             Register List Evaluation

//      3. REG_LIST             Register List Evaluation

//

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module REG_LIST ( DIN, IPOS, INIT, OPOS, VALID);

module REG_LIST ( DIN, IPOS, INIT, OPOS, VALID);

        // Detects set bits in register list for SAVE/RESTORE & ENTER/EXIT

        // Detects set bits in register list for SAVE/RESTORE & ENTER/EXIT

        input    [7:0]   DIN;

        input    [7:0]   DIN;

        input    [2:0]   IPOS;

        input    [2:0]   IPOS;

        input                   INIT;

        input                   INIT;

        output   [2:0]   OPOS;

        output   [2:0]   OPOS;

        output                  VALID;

        output                  VALID;

        reg              [7:1]  filter;

        reg              [7:1]  filter;

        wire     [7:0]   mdat_0;

        wire     [7:0]   mdat_0;

        wire     [3:0]   mdat_1;

        wire     [3:0]   mdat_1;

        wire     [1:0]   mdat_2;

        wire     [1:0]   mdat_2;

        always @(IPOS or DIN)

        always @(IPOS or DIN)

                case (IPOS)

                case (IPOS)

                  3'd0 : filter =  DIN[7:1];

                  3'd0 : filter =  DIN[7:1];

                  3'd1 : filter = {DIN[7:2],1'b0};

                  3'd1 : filter = {DIN[7:2],1'b0};

                  3'd2 : filter = {DIN[7:3],2'b0};

                  3'd2 : filter = {DIN[7:3],2'b0};

                  3'd3 : filter = {DIN[7:4],3'b0};

                  3'd3 : filter = {DIN[7:4],3'b0};

                  3'd4 : filter = {DIN[7:5],4'b0};

                  3'd4 : filter = {DIN[7:5],4'b0};

                  3'd5 : filter = {DIN[7:6],5'b0};

                  3'd5 : filter = {DIN[7:6],5'b0};

                  3'd6 : filter = {DIN[7]  ,6'b0};

                  3'd6 : filter = {DIN[7]  ,6'b0};

                  3'd7 : filter =           7'b0;

                  3'd7 : filter =           7'b0;

                endcase

                endcase

        assign mdat_0  = INIT ? DIN : {filter,1'b0};

        assign mdat_0  = INIT ? DIN : {filter,1'b0};

        assign OPOS[2] = (mdat_0[3:0] == 4'h0);

        assign OPOS[2] = (mdat_0[3:0] == 4'h0);

        assign mdat_1  = OPOS[2] ? mdat_0[7:4] : mdat_0[3:0];

        assign mdat_1  = OPOS[2] ? mdat_0[7:4] : mdat_0[3:0];

        assign OPOS[1] = (mdat_1[1:0] == 2'b00);

        assign OPOS[1] = (mdat_1[1:0] == 2'b00);

        assign mdat_2  = OPOS[1] ? mdat_1[3:2] : mdat_1[1:0];

        assign mdat_2  = OPOS[1] ? mdat_1[3:2] : mdat_1[1:0];

        assign OPOS[0] = ~mdat_2[0];

        assign OPOS[0] = ~mdat_2[0];

        assign VALID   = (mdat_2 != 2'b00);

        assign VALID   = (mdat_2 != 2'b00);

endmodule

endmodule

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

//

//      4. ILL_UNDEF    Illegal and Undefined Opcodes Detection

//      4. ILL_UNDEF    Illegal and Undefined Opcodes Detection

//

//

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module ILL_UNDEF (OPREG, ANZ_VAL, USER, CFG, ILL, UNDEF );

module ILL_UNDEF (OPREG, ANZ_VAL, USER, CFG, ILL, UNDEF );

        input   [23:0]   OPREG;

        input   [23:0]   OPREG;

        input    [2:0]   ANZ_VAL;

        input    [2:0]   ANZ_VAL;

        input    [3:1]  CFG;            // 3=CUSTOM,2=MMU,1=FPU

        input    [3:1]  CFG;            // 3=CUSTOM,2=MMU,1=FPU

        input                   USER;

        input                   USER;

        output  reg             ILL;

        output  reg             ILL;

        output                  UNDEF;

        output                  UNDEF;

        reg                             undef_opc;

        reg                             undef_opc;

        reg                             undef_am;

        reg                             undef_am;

        reg                             undef_im;

        reg                             undef_im;

        wire     [2:0]   valid;

        wire     [2:0]   valid;

        wire                    gen12,gen22,gen13,gen23;

        wire                    gen12,gen22,gen13,gen23;

        wire                    igen12,igen22,igen13,igen23;

        wire                    igen12,igen22,igen13,igen23;

        wire                    lsbes;

        wire                    lsbes;

        parameter udef_amode = 5'b10011;        // Undefined Addressing Mode

        parameter udef_amode = 5'b10011;        // Undefined Addressing Mode

        parameter imode          = 5'b10100;    // Immediate Addressing Mode 

        parameter imode          = 5'b10100;    // Immediate Addressing Mode 

        // [2]= minimum 3, [1]= minimum 2, [0]=minimum 1

        // [2]= minimum 3, [1]= minimum 2, [0]=minimum 1

        assign valid = {(ANZ_VAL[2] | (ANZ_VAL[1:0] == 2'b11)),(ANZ_VAL[2:1] != 2'b00),(ANZ_VAL != 3'b000)};

        assign valid = {(ANZ_VAL[2] | (ANZ_VAL[1:0] == 2'b11)),(ANZ_VAL[2:1] != 2'b00),(ANZ_VAL != 3'b000)};

        assign lsbes = (OPREG[1:0] == 2'b10);    // Tag of all 3 Byte opcodes

        assign lsbes = (OPREG[1:0] == 2'b10);    // Tag of all 3 Byte opcodes

        // +++++++++++++++++++++++++  Detect illegale opcodes  +++++++++++++++++++

        // +++++++++++++++++++++++++  Detect illegale opcodes  +++++++++++++++++++

        always @(OPREG or lsbes or valid or USER)

        always @(OPREG or lsbes or valid or USER)

                casex ({valid[2:1],OPREG[13:2],lsbes})

                casex ({valid[2:1],OPREG[13:2],lsbes})

                  15'bx1_xx_x000_1x10_11_0 : ILL = USER;        // SPRi/LPRi DCR

                  15'bx1_xx_x000_1x10_11_0 : ILL = USER;        // SPRi/LPRi DCR

                  15'bx1_xx_x001_xx10_11_0 : ILL = USER;        // SPRi/LPRi BPC/DSR

                  15'bx1_xx_x001_xx10_11_0 : ILL = USER;        // SPRi/LPRi BPC/DSR

                  15'bx1_xx_xx10_xx10_11_0 : ILL = USER;        // SPRi/LPRi CAR/CFG/PSR

                  15'bx1_xx_xx10_xx10_11_0 : ILL = USER;        // SPRi/LPRi CAR/CFG/PSR

                  15'bx1_xx_x101_1x10_11_0 : ILL = USER;        // SPRi/LPRi USP

                  15'bx1_xx_x101_1x10_11_0 : ILL = USER;        // SPRi/LPRi USP

                  15'bx1_xx_x111_0x10_11_0 : ILL = USER;        // SPRi/LPRi INTBASE

                  15'bx1_xx_x111_0x10_11_0 : ILL = USER;        // SPRi/LPRi INTBASE

                  15'bx1_xx_x0x1_0111_11_x : ILL = USER & OPREG[0];      // BICPSRW,BISPSRW

                  15'bx1_xx_x0x1_0111_11_x : ILL = USER & OPREG[0];      // BICPSRW,BISPSRW

                  15'bx1_00_10xx_0000_11_1 : ILL = USER;        // SETCFG - Achtung : is coded as 2 Byte Opcode 

                  15'bx1_00_10xx_0000_11_1 : ILL = USER;        // SETCFG - Achtung : is coded as 2 Byte Opcode 

                  15'b1x_00_xxxx_0001_11_1 : ILL = USER;        // LMR/SMR/RDVAL/WRVAL

                  15'b1x_00_xxxx_0001_11_1 : ILL = USER;        // LMR/SMR/RDVAL/WRVAL

                  15'b1x_10_01xx_0001_11_1 : ILL = USER;        // CINV

                  15'b1x_10_01xx_0001_11_1 : ILL = USER;        // CINV

                  default                                  : ILL = 1'b0;

                  default                                  : ILL = 1'b0;

                endcase

                endcase

        // ++++++++++++++++++++++++ Detect Undefined opcodes  +++++++++++++++

        // ++++++++++++++++++++++++ Detect Undefined opcodes  +++++++++++++++

        always @(OPREG or lsbes or valid or CFG)

        always @(OPREG or lsbes or valid or CFG)

                casex ({valid,OPREG[13:2],lsbes})

                casex ({valid,OPREG[13:2],lsbes})

                  16'bx1x_xx_xxxx_1111_110 : undef_opc = 1'b1;          // Format 3 : xxx1

                  16'bx1x_xx_xxxx_1111_110 : undef_opc = 1'b1;          // Format 3 : xxx1

                  16'bx1x_xx_x100_0111_110 : undef_opc = 1'b1;          // Format 3 : 1000

                  16'bx1x_xx_x100_0111_110 : undef_opc = 1'b1;          // Format 3 : 1000

                  16'b1xx_1x_xxxx_0000_111 : undef_opc = 1'b1;          // Format 5 : 1xxx

                  16'b1xx_1x_xxxx_0000_111 : undef_opc = 1'b1;          // Format 5 : 1xxx

                  16'b1xx_01_xxxx_0000_111 : undef_opc = 1'b1;          // Format 5 : 01xx

                  16'b1xx_01_xxxx_0000_111 : undef_opc = 1'b1;          // Format 5 : 01xx

                  16'b1xx_01_00xx_0100_111 : undef_opc = 1'b1;          // Format 6 : 0100

                  16'b1xx_01_00xx_0100_111 : undef_opc = 1'b1;          // Format 6 : 0100

                  16'b1xx_10_10xx_x100_111 : undef_opc = 1'b1;          // Format 6/7 : 1010

                  16'b1xx_10_10xx_x100_111 : undef_opc = 1'b1;          // Format 6/7 : 1010

                  16'b1xx_xx_xxxx_x011_111 : undef_opc = ~CFG[1];       // Format 9/11 : FPU Befehle wie MOVif etc. und ADDf etc.

                  16'b1xx_xx_xxxx_x011_111 : undef_opc = ~CFG[1];       // Format 9/11 : FPU Befehle wie MOVif etc. und ADDf etc.

                  16'b1xx_xx_xxxx_1111_111 : undef_opc = ~CFG[1];       // Format 12 : FPU Befehle wie POLYf etc.

                  16'b1xx_xx_xxxx_1111_111 : undef_opc = ~CFG[1];       // Format 12 : FPU Befehle wie POLYf etc.

                  16'b1xx_x1_xxxx_0001_111 : undef_opc = 1'b1;          // Format 14 : x1xx 

                  16'b1xx_x1_xxxx_0001_111 : undef_opc = 1'b1;          // Format 14 : x1xx 

                  16'b1xx_10_00xx_0001_111 : undef_opc = 1'b1;          // Format 14 : 1000

                  16'b1xx_10_00xx_0001_111 : undef_opc = 1'b1;          // Format 14 : 1000

                  16'b1xx_10_1xxx_0001_111 : undef_opc = 1'b1;          // Format 14 : 101x

                  16'b1xx_10_1xxx_0001_111 : undef_opc = 1'b1;          // Format 14 : 101x

                  16'b1xx_00_1xxx_0001_111 : undef_opc = ~CFG[2] | ~OPREG[18];  // Format 14 : LMR/SMR

                  16'b1xx_00_1xxx_0001_111 : undef_opc = ~CFG[2] | ~OPREG[18];  // Format 14 : LMR/SMR

                  16'b1xx_xx_xxxx_x011_011 : undef_opc = ~CFG[3];       // Format 15.1/15.5 : CUSTOM CCV0, CCAL0 etc.

                  16'b1xx_xx_xxxx_x011_011 : undef_opc = ~CFG[3];       // Format 15.1/15.5 : CUSTOM CCV0, CCAL0 etc.

                  16'b1xx_xx_xxxx_0001_011 : undef_opc = 1'b1;          // Format 15.0 - not yet in, requires HW change

                  16'b1xx_xx_xxxx_0001_011 : undef_opc = 1'b1;          // Format 15.0 - not yet in, requires HW change

                  16'b1xx_xx_xxxx_x1x1_011 : undef_opc = 1'b1;          // Format 15 : rest

                  16'b1xx_xx_xxxx_x1x1_011 : undef_opc = 1'b1;          // Format 15 : rest

                  16'b1xx_xx_xxxx_1001_011 : undef_opc = 1'b1;          // Format 15.4

                  16'b1xx_xx_xxxx_1001_011 : undef_opc = 1'b1;          // Format 15.4

                // completely undefined :

                // completely undefined :

                  16'bxx1_xx_xxxx_0111_111 : undef_opc = 1'b1;          // Format 10

                  16'bxx1_xx_xxxx_0111_111 : undef_opc = 1'b1;          // Format 10

                  16'bxx1_xx_xxxx_100x_111 : undef_opc = 1'b1;          // Format 13/18

                  16'bxx1_xx_xxxx_100x_111 : undef_opc = 1'b1;          // Format 13/18

                  16'bxx1_xx_xxxx_x101_111 : undef_opc = 1'b1;          // Format 16/17

                  16'bxx1_xx_xxxx_x101_111 : undef_opc = 1'b1;          // Format 16/17

                  16'bxx1_xx_xxxx_xxx0_011 : undef_opc = 1'b1;          // Format 19

                  16'bxx1_xx_xxxx_xxx0_011 : undef_opc = 1'b1;          // Format 19

                  default                                  : undef_opc = 1'b0;

                  default                                  : undef_opc = 1'b0;

                endcase

                endcase

        // 2. Undefined Addressing mode 5'b10011

        // 2. Undefined Addressing mode 5'b10011

        assign gen12 = (OPREG[15:11] == udef_amode);

        assign gen12 = (OPREG[15:11] == udef_amode);

        assign gen22 = (OPREG[10:6]  == udef_amode);

        assign gen22 = (OPREG[10:6]  == udef_amode);

        assign gen13 = (OPREG[23:19] == udef_amode);

        assign gen13 = (OPREG[23:19] == udef_amode);

        assign gen23 = (OPREG[18:14] == udef_amode);

        assign gen23 = (OPREG[18:14] == udef_amode);

        always @(OPREG or valid or gen12 or gen22 or gen13 or gen23)

        always @(OPREG or valid or gen12 or gen22 or gen13 or gen23)

                if (valid[2] && (OPREG[7:5] != 3'b000) && (OPREG[3:0] == 4'b1110)) undef_am = gen13 | gen23;     // nearly all 3 Byte opcodes

                if (valid[2] && (OPREG[7:5] != 3'b000) && (OPREG[3:0] == 4'b1110)) undef_am = gen13 | gen23;     // nearly all 3 Byte opcodes