// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: TOP_MISC.v
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// Filename: TOP_MISC.v
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// Version: 1.0
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// Version: 2.0
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// Date: 30 May 2015
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// History: 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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//
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//
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// Copyright (C) 2015 Udo Moeller
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// Copyright (C) 2016 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// This source file is free software; you can redistribute it
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// either version 2.1 of the License, or (at your option) any
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// later version.
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// later version.
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//
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//
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// This source is distributed in the hope that it will be
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE. See the GNU Lesser General Public License for more
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// PURPOSE. See the GNU Lesser General Public License for more
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// details.
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// details.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// 1. IO_SWITCH Switch between ICACHE and DCACHE to IO Path
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// 1. IO_SWITCH Switch between ICACHE and DCACHE to IO Path
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// 2. MAKE_STAT Generate Statistic Signals
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// 2. MAKE_STAT Generate Statistic Signals
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 1. IO_SWITCH Switch between ICACHE and DCACHE to IO Path
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// 1. IO_SWITCH Switch between ICACHE and DCACHE to IO Path
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module IO_SWITCH ( BCLK, BRESET, I_IOA, D_IOA, I_IORD, D_IORD, D_IOWR, IO_READY, GENSTAT, D_IOBE, ILO_SIG, DCWACC,
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module IO_SWITCH ( BCLK, BRESET, I_IOA, D_IOA, I_IORD, D_IORD, D_IOWR, IO_READY, GENSTAT, D_IOBE, ILO_SIG, DCWACC,
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IO_A, IO_RD, IO_WR, IO_BE, I_IORDY, D_IORDY, STATUS, ILO );
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IO_A, IO_RD, IO_WR, IO_BE, I_IORDY, D_IORDY, STATUS, ILO );
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input BCLK,BRESET;
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input BCLK,BRESET;
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input [31:0] I_IOA,D_IOA;
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input [31:0] I_IOA,D_IOA;
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input I_IORD;
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input I_IORD;
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input D_IORD,D_IOWR;
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input D_IORD,D_IOWR;
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input [3:0] D_IOBE;
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input [3:0] D_IOBE;
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input IO_READY;
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input IO_READY;
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input [2:0] GENSTAT;
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input [2:0] GENSTAT;
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input ILO_SIG;
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input ILO_SIG;
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input [1:0] DCWACC;
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input [1:0] DCWACC;
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output [31:0] IO_A;
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output [31:0] IO_A;
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output IO_RD,IO_WR;
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output IO_RD,IO_WR;
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output [3:0] IO_BE;
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output [3:0] IO_BE;
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output I_IORDY;
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output I_IORDY;
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output D_IORDY;
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output D_IORDY;
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output [3:0] STATUS;
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output [3:0] STATUS;
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output ILO;
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output ILO;
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reg [3:0] STATUS;
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reg [3:0] STATUS;
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reg [1:0] select;
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reg [1:0] select;
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reg ilo_flag;
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reg ilo_flag;
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wire daten;
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wire daten;
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wire sel_dp;
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wire sel_dp;
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wire interrupt;
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wire interrupt;
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wire ilo_keep;
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wire ilo_keep;
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assign daten = D_IORD | D_IOWR;
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assign daten = D_IORD | D_IOWR;
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// DCACHE has priority.
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// DCACHE has priority.
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always @(posedge BCLK or negedge BRESET)
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always @(posedge BCLK or negedge BRESET)
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if (!BRESET) select <= 2'b0;
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if (!BRESET) select <= 2'b0;
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else
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else
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casex ({I_IORD,D_IORD,D_IOWR,IO_READY,ilo_keep,select})
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casex ({I_IORD,D_IORD,D_IOWR,IO_READY,ilo_keep,select})
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7'b000xx_00 : select <= 2'b00;
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7'b000xx_00 : select <= 2'b00;
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7'b1000x_00 : select <= 2'b11;
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7'b1000x_00 : select <= 2'b11;
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7'bx100x_00 : select <= 2'b10;
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7'bx100x_00 : select <= 2'b10;
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7'bxx10x_00 : select <= 2'b10;
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7'bxx10x_00 : select <= 2'b10;
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// the access has in the same cycle a READY !
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// the access has in the same cycle a READY !
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7'b1001x_00 : select <= 2'b00;
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7'b1001x_00 : select <= 2'b00;
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7'bx101x_00 : select <= 2'b00;
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7'bx101x_00 : select <= 2'b00;
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7'bxx11x_00 : select <= 2'b00;
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7'bxx11x_00 : select <= 2'b00;
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// Datea Access
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// Datea Access
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7'bxxx0x_10 : select <= 2'b10;
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7'bxxx0x_10 : select <= 2'b10;
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7'bxxx11_10 : select <= 2'b10; // keep because of Interlocked
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7'bxxx11_10 : select <= 2'b10; // keep because of Interlocked
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7'bxxx10_10 : select <= 2'b00;
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7'bxxx10_10 : select <= 2'b00;
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// Instruction Access
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// Instruction Access
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7'bxxx0x_11 : select <= 2'b11;
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7'bxxx0x_11 : select <= 2'b11;
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7'bxxx1x_11 : select <= 2'b00;
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7'bxxx1x_11 : select <= 2'b00;
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default : select <= 2'b00;
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default : select <= 2'b00;
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endcase
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endcase
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assign sel_dp = (select == 2'b10) | ((select == 2'b00) & daten);
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assign sel_dp = (select == 2'b10) | ((select == 2'b00) & daten);
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assign IO_RD = sel_dp ? D_IORD : I_IORD;
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assign IO_RD = sel_dp ? D_IORD : I_IORD;
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assign IO_WR = sel_dp ? D_IOWR : 1'b0;
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assign IO_WR = sel_dp ? D_IOWR : 1'b0;
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assign IO_A = sel_dp ? D_IOA : I_IOA;
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assign IO_A = sel_dp ? D_IOA : I_IOA;
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assign IO_BE = sel_dp ? D_IOBE : 4'b1111; // Instruction read always 32 Bit
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assign IO_BE = sel_dp ? D_IOBE : 4'b1111; // Instruction read always 32 Bit
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assign D_IORDY = sel_dp & IO_READY;
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assign D_IORDY = sel_dp & IO_READY;
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assign I_IORDY = ~sel_dp & IO_READY;
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assign I_IORDY = ~sel_dp & IO_READY;
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assign interrupt = GENSTAT[1] | GENSTAT[0];
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assign interrupt = GENSTAT[1] | GENSTAT[0];
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always @(*)
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always @(*)
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casex ({sel_dp,daten,interrupt,I_IORD})
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casex ({sel_dp,daten,interrupt,I_IORD})
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4'b110x : STATUS = 4'hA; // Daten
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4'b110x : STATUS = 4'hA; // Daten
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4'b111x : STATUS = GENSTAT[1] ? 4'h4 : 4'h6; // Int Ack. : End of Int
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4'b111x : STATUS = GENSTAT[1] ? 4'h4 : 4'h6; // Int Ack. : End of Int
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4'b0xx1 : STATUS = 4'h8; // Programm
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4'b0xx1 : STATUS = 4'h8; // Programm
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default : STATUS = {3'd0,GENSTAT[2]}; // WAIT or Inactive
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default : STATUS = {3'd0,GENSTAT[2]}; // WAIT or Inactive
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endcase
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endcase
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// +++++++++++ ILO Control ++++++++++++++++++
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// +++++++++++ ILO Control ++++++++++++++++++
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always @(posedge BCLK)
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always @(posedge BCLK)
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if (!ILO_SIG) ilo_flag <= 1'b0; // Flag is set at read and cleared with write
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if (!ILO_SIG) ilo_flag <= 1'b0; // Flag is set at read and cleared with write
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else ilo_flag <= (D_IORD & sel_dp) | DCWACC[0] | ilo_keep;
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else ilo_flag <= (D_IORD & sel_dp) | DCWACC[0] | ilo_keep;
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assign ilo_keep = ilo_flag & ~D_IOWR & ~DCWACC[1];
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assign ilo_keep = ilo_flag & ~D_IOWR & ~DCWACC[1];
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assign ILO = ILO_SIG & ((D_IORD & sel_dp) | DCWACC[0] | ilo_flag | D_IOWR | DCWACC[1]);
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assign ILO = ILO_SIG & ((D_IORD & sel_dp) | DCWACC[0] | ilo_flag | D_IOWR | DCWACC[1]);
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endmodule
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endmodule
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// 2. MAKE_STAT Generate Statistic Signals
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// 2. MAKE_STAT Generate Statistic Signals
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module MAKE_STAT ( BCLK, READ, DACC_OK, DC_ACC, DPTE_ACC, DC_MDONE, DRAM_WR, IC_READ, IACC_OK, DATA_HOLD,
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module MAKE_STAT ( BCLK, READ, DACC_OK, DC_ACC, DPTE_ACC, DC_MDONE, DRAM_WR, IC_READ, IACC_OK, DATA_HOLD,
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IC_ACC, IPTE_ACC, IC_MDONE, KOLLISION, STATSIGS );
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IC_ACC, IPTE_ACC, IC_MDONE, KOLLISION, STATSIGS );
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input BCLK;
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input BCLK;
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input READ,DACC_OK;
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input READ,DACC_OK;
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input DC_ACC,DPTE_ACC,DC_MDONE;
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input DC_ACC,DPTE_ACC,DC_MDONE;
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input DRAM_WR;
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input DRAM_WR;
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input IC_READ,IACC_OK,DATA_HOLD;
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input IC_READ,IACC_OK,DATA_HOLD;
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input IC_ACC,IPTE_ACC,IC_MDONE;
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input IC_ACC,IPTE_ACC,IC_MDONE;
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input KOLLISION;
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input KOLLISION;
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output reg [7:0] STATSIGS;
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output reg [7:0] STATSIGS;
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always @(posedge BCLK)
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always @(posedge BCLK)
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begin
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begin
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STATSIGS[7] <= KOLLISION; // 7 : from ICACHE : collisions
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STATSIGS[7] <= KOLLISION; // 7 : from ICACHE : collisions
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STATSIGS[6] <= IPTE_ACC; // 6 : Instruction PTE access
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STATSIGS[6] <= IPTE_ACC; // 6 : Instruction PTE access
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STATSIGS[5] <= IC_ACC & IC_MDONE; // 5 : Instruction Memory read
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STATSIGS[5] <= IC_ACC & IC_MDONE; // 5 : Instruction Memory read
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STATSIGS[4] <= IC_READ & IACC_OK & ~DATA_HOLD; // 4 : Instruction read , can be IO-Port too !
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STATSIGS[4] <= IC_READ & IACC_OK & ~DATA_HOLD; // 4 : Instruction read , can be IO-Port too !
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STATSIGS[3] <= DRAM_WR; // 3 : Data write
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STATSIGS[3] <= DRAM_WR; // 3 : Data write
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STATSIGS[2] <= DPTE_ACC; // 2 : Data PTE access
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STATSIGS[2] <= DPTE_ACC; // 2 : Data PTE access
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STATSIGS[1] <= DC_ACC & DC_MDONE; // 1 : Data Memory read
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STATSIGS[1] <= DC_ACC & DC_MDONE; // 1 : Data Memory read
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STATSIGS[0] <= READ & DACC_OK; // 0 : Data read , can be IO-Port too !
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STATSIGS[0] <= READ & DACC_OK; // 0 : Data read , can be IO-Port too !
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end
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end
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endmodule
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endmodule
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