-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Copyright (C) 2009 Sam Green
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-- Copyright (C) 2009 Sam Green
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--
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--
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-- This code is free software; you can redistribute it and/or
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-- This code is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- version 2.1 of the License, or (at your option) any later version.
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--
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--
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-- This code is distributed in the hope that it will be useful,
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- Lesser General Public License for more details.
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--
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--
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--
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--
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-- Revision Date Author Comment
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-- Revision Date Author Comment
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-- -------- ---------- -------------------- ----------------
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-- -------- ---------- -------------------- ----------------
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-- 1.0 09/06/09 S. Green Initial version
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-- 1.0 09/06/09 S. Green Initial version
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.globals.all;
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use work.globals.all;
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entity manchesterWireless is
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entity manchesterWireless is
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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rst_i : in std_logic;
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rst_i : in std_logic;
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data_i : in std_logic;
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data_i : in std_logic;
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q_o : out std_logic_vector(WORD_LENGTH-1 downto 0);
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q_o : out std_logic_vector(WORD_LENGTH-1 downto 0);
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ready_o : out std_logic;
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ready_o : out std_logic;
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recieved_debug : out std_logic_vector(3 downto 0);
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recieved_debug : out std_logic_vector(3 downto 0);
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waitforstart_rdy : out std_logic
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waitforstart_rdy : out std_logic
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);
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);
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end;
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end;
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architecture behavioral of manchesterWireless is
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architecture behavioral of manchesterWireless is
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component waitForStart
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component waitForStart
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port (
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port (
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data_i : in std_logic;
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data_i : in std_logic;
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clk_i : in std_logic;
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clk_i : in std_logic;
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rst_i : in std_logic;
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rst_i : in std_logic;
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ready_o : out std_logic
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ready_o : out std_logic
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);
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);
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end component;
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end component;
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component singleDouble
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component singleDouble
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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ce_i : in std_logic;
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ce_i : in std_logic;
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rst_i : in std_logic;
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rst_i : in std_logic;
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data_i : in std_logic;
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data_i : in std_logic;
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q_o : out std_logic_vector(3 downto 0);
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q_o : out std_logic_vector(3 downto 0);
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ready_o : out std_logic
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ready_o : out std_logic
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);
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);
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end component;
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end component;
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component decode
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component decode
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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rst_i : in std_logic;
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rst_i : in std_logic;
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nd_i : in std_logic;
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nd_i : in std_logic;
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encoded_i : in std_logic_vector(3 downto 0);
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encoded_i : in std_logic_vector(3 downto 0);
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decoded_o : out std_logic_vector(WORD_LENGTH-1 downto 0);
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decoded_o : out std_logic_vector(WORD_LENGTH-1 downto 0);
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nd_o : out std_logic
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nd_o : out std_logic
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);
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);
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end component;
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end component;
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signal wait_rdy : std_logic;
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signal wait_rdy : std_logic;
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signal md16_nd : std_logic;
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signal md16_nd : std_logic;
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signal md16_q_o : std_logic_vector(3 downto 0);
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signal md16_q_o : std_logic_vector(3 downto 0);
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begin
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begin
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inst_waitForStart: waitForStart
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inst_waitForStart: waitForStart
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port map(
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port map(
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data_i => data_i,
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data_i => data_i,
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clk_i => clk_i,
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clk_i => clk_i,
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rst_i => rst_i,
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rst_i => rst_i,
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ready_o => wait_rdy
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ready_o => wait_rdy
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);
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);
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waitforstart_rdy <= wait_rdy;
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waitforstart_rdy <= wait_rdy;
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inst_singleDouble : singleDouble
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inst_singleDouble : singleDouble
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port map(
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port map(
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clk_i => clk_i,
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clk_i => clk_i,
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ce_i => wait_rdy,
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ce_i => wait_rdy,
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rst_i => rst_i,
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rst_i => rst_i,
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data_i => data_i,
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data_i => data_i,
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q_o => md16_q_o,
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q_o => md16_q_o,
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ready_o => md16_nd
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ready_o => md16_nd
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);
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);
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recieved_debug <= md16_q_o;
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recieved_debug <= md16_q_o;
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inst_decode: decode
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inst_decode: decode
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port map(
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port map(
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clk_i => clk_i,
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clk_i => clk_i,
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rst_i => rst_i,
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rst_i => rst_i,
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nd_i => md16_nd,
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nd_i => md16_nd,
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encoded_i => md16_q_o,
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encoded_i => md16_q_o,
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decoded_o => q_o,
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decoded_o => q_o,
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nd_o => ready_o
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nd_o => ready_o
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);
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);
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end;
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end;
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