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[/] [marca/] [tags/] [INITIAL/] [vhdl/] [code_memory.vhd] - Diff between revs 3 and 8

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Rev 3 Rev 8
-- megafunction wizard: %ROM: 1-PORT%
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- VERSION: WM1.0
-- MODULE: altsyncram 
-- MODULE: altsyncram 
 
 
-- ============================================================
-- ============================================================
-- File Name: code_memory.vhd
-- File Name: code_memory.vhd
-- Megafunction Name(s):
-- Megafunction Name(s):
--                      altsyncram
--                      altsyncram
-- ============================================================
-- ============================================================
-- ************************************************************
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition
-- 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition
-- ************************************************************
-- ************************************************************
 
 
 
 
--Copyright (C) 1991-2006 Altera Corporation
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions 
--Your use of Altera Corporation's design tools, logic functions 
--and other software and tools, and its AMPP partner logic 
--and other software and tools, and its AMPP partner logic 
--functions, and any output files any of the foregoing 
--functions, and any output files any of the foregoing 
--(including device programming or simulation files), and any 
--(including device programming or simulation files), and any 
--associated documentation or information are expressly subject 
--associated documentation or information are expressly subject 
--to the terms and conditions of the Altera Program License 
--to the terms and conditions of the Altera Program License 
--Subscription Agreement, Altera MegaCore Function License 
--Subscription Agreement, Altera MegaCore Function License 
--Agreement, or other applicable license agreement, including, 
--Agreement, or other applicable license agreement, including, 
--without limitation, that your use is for the sole purpose of 
--without limitation, that your use is for the sole purpose of 
--programming logic devices manufactured by Altera and sold by 
--programming logic devices manufactured by Altera and sold by 
--Altera or its authorized distributors.  Please refer to the 
--Altera or its authorized distributors.  Please refer to the 
--applicable agreement for further details.
--applicable agreement for further details.
 
 
 
 
LIBRARY ieee;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_1164.all;
 
 
LIBRARY altera_mf;
LIBRARY altera_mf;
USE altera_mf.all;
USE altera_mf.all;
 
 
ENTITY code_memory IS
ENTITY code_memory IS
        GENERIC
        GENERIC
        (
        (
                init_file       : STRING
                init_file       : STRING
        );
        );
        PORT
        PORT
        (
        (
                address         : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
                address         : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
                clken           : IN STD_LOGIC ;
                clken           : IN STD_LOGIC ;
                clock           : IN STD_LOGIC ;
                clock           : IN STD_LOGIC ;
                q               : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
                q               : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
        );
        );
END code_memory;
END code_memory;
 
 
 
 
ARCHITECTURE SYN OF code_memory IS
ARCHITECTURE SYN OF code_memory IS
 
 
        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (15 DOWNTO 0);
        SIGNAL sub_wire0        : STD_LOGIC_VECTOR (15 DOWNTO 0);
 
 
 
 
 
 
        COMPONENT altsyncram
        COMPONENT altsyncram
        GENERIC (
        GENERIC (
                address_aclr_a          : STRING;
                address_aclr_a          : STRING;
                init_file               : STRING;
                init_file               : STRING;
                intended_device_family          : STRING;
                intended_device_family          : STRING;
                lpm_hint                : STRING;
                lpm_hint                : STRING;
                lpm_type                : STRING;
                lpm_type                : STRING;
                numwords_a              : NATURAL;
                numwords_a              : NATURAL;
                operation_mode          : STRING;
                operation_mode          : STRING;
                outdata_aclr_a          : STRING;
                outdata_aclr_a          : STRING;
                outdata_reg_a           : STRING;
                outdata_reg_a           : STRING;
                widthad_a               : NATURAL;
                widthad_a               : NATURAL;
                width_a         : NATURAL;
                width_a         : NATURAL;
                width_byteena_a         : NATURAL
                width_byteena_a         : NATURAL
        );
        );
        PORT (
        PORT (
                        clocken0        : IN STD_LOGIC ;
                        clocken0        : IN STD_LOGIC ;
                        clock0  : IN STD_LOGIC ;
                        clock0  : IN STD_LOGIC ;
                        address_a       : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
                        address_a       : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
                        q_a     : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
                        q_a     : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
        );
        );
        END COMPONENT;
        END COMPONENT;
 
 
BEGIN
BEGIN
        q    <= sub_wire0(15 DOWNTO 0);
        q    <= sub_wire0(15 DOWNTO 0);
 
 
        altsyncram_component : altsyncram
        altsyncram_component : altsyncram
        GENERIC MAP (
        GENERIC MAP (
                address_aclr_a => "NONE",
                address_aclr_a => "NONE",
                init_file => init_file,
                init_file => init_file,
                intended_device_family => "Cyclone",
                intended_device_family => "Cyclone",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_hint => "ENABLE_RUNTIME_MOD=NO",
                lpm_type => "altsyncram",
                lpm_type => "altsyncram",
                numwords_a => 8192,
                numwords_a => 8192,
                operation_mode => "ROM",
                operation_mode => "ROM",
                outdata_aclr_a => "NONE",
                outdata_aclr_a => "NONE",
                outdata_reg_a => "UNREGISTERED",
                outdata_reg_a => "UNREGISTERED",
                widthad_a => 13,
                widthad_a => 13,
                width_a => 16,
                width_a => 16,
                width_byteena_a => 1
                width_byteena_a => 1
        )
        )
        PORT MAP (
        PORT MAP (
                clocken0 => clken,
                clocken0 => clken,
                clock0 => clock,
                clock0 => clock,
                address_a => address,
                address_a => address,
                q_a => sub_wire0
                q_a => sub_wire0
        );
        );
 
 
 
 
 
 
END SYN;
END SYN;
 
 
-- ============================================================
-- ============================================================
-- CNX file retrieval info
-- CNX file retrieval info
-- ============================================================
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: Clken NUMERIC "1"
-- Retrieval info: PRIVATE: Clken NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "src/code.mif"
-- Retrieval info: PRIVATE: MIFfilename STRING "src/code.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
-- Retrieval info: PRIVATE: WidthData NUMERIC "16"
-- Retrieval info: PRIVATE: WidthData NUMERIC "16"
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: INIT_FILE STRING "src/code.mif"
-- Retrieval info: CONSTANT: INIT_FILE STRING "src/code.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[12..0]
-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL address[12..0]
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL code_memory.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL code_memory.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL code_memory.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL code_memory.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL code_memory.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL code_memory.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL code_memory.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL code_memory.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL code_memory_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL code_memory_inst.vhd FALSE
 
 

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