-- This file is part of the marca processor.
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-- This file is part of the marca processor.
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- This program is free software; you can redistribute it and/or modify it
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-- This program is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU Library General Public License as published
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-- under the terms of the GNU Library General Public License as published
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- any later version.
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-- any later version.
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Library General Public License for more details.
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-- Library General Public License for more details.
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|
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-- You should have received a copy of the GNU Library General Public
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-- You should have received a copy of the GNU Library General Public
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-- License along with this program; if not, write to the Free Software
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-- License along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- MARCA decode stage
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-- MARCA decode stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- architecture for the instruction-decode pipeline stage
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-- architecture for the instruction-decode pipeline stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Wolfgang Puffitsch
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-- Wolfgang Puffitsch
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-- Computer Architecture Lab, Group 3
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-- Computer Architecture Lab, Group 3
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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|
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use work.marca_pkg.all;
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use work.marca_pkg.all;
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|
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architecture behaviour of decode is
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architecture behaviour of decode is
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|
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signal pc_reg : std_logic_vector(REG_WIDTH-1 downto 0);
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signal pc_reg : std_logic_vector(REG_WIDTH-1 downto 0);
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signal dest_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
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signal dest_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
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signal instr_reg : std_logic_vector(PDATA_WIDTH-1 downto 0);
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signal instr_reg : std_logic_vector(PDATA_WIDTH-1 downto 0);
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|
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signal src1_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
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signal src1_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
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signal src2_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
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signal src2_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
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component regfile is
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component regfile is
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port (
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port (
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clock : in std_logic;
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clock : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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hold : in std_logic;
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hold : in std_logic;
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rd1_addr : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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rd1_addr : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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rd2_addr : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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rd2_addr : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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rd1_val : out std_logic_vector(REG_WIDTH-1 downto 0);
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rd1_val : out std_logic_vector(REG_WIDTH-1 downto 0);
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rd2_val : out std_logic_vector(REG_WIDTH-1 downto 0);
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rd2_val : out std_logic_vector(REG_WIDTH-1 downto 0);
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wr_ena : in std_logic;
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wr_ena : in std_logic;
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wr_addr : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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wr_addr : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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wr_val : in std_logic_vector(REG_WIDTH-1 downto 0));
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wr_val : in std_logic_vector(REG_WIDTH-1 downto 0));
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end component;
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end component;
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begin -- behaviour
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begin -- behaviour
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regfile_unit : regfile
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regfile_unit : regfile
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port map (
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port map (
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clock => clock,
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clock => clock,
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reset => reset,
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reset => reset,
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hold => hold,
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hold => hold,
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rd1_addr => src1_reg,
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rd1_addr => src1_reg,
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rd2_addr => src2_reg,
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rd2_addr => src2_reg,
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rd1_val => op1,
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rd1_val => op1,
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rd2_val => op2,
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rd2_val => op2,
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wr_ena => wr_ena,
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wr_ena => wr_ena,
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wr_addr => wr_dest,
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wr_addr => wr_dest,
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wr_val => wr_val);
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wr_val => wr_val);
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syn_proc: process (clock, reset)
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syn_proc: process (clock, reset)
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begin -- process syn_proc
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begin -- process syn_proc
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if reset = RESET_ACTIVE then -- asynchronous reset (active low)
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if reset = RESET_ACTIVE then -- asynchronous reset (active low)
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pc_reg <= (others => '0');
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pc_reg <= (others => '0');
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dest_reg <= (others => '0');
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dest_reg <= (others => '0');
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instr_reg <= OPC_PFX_C & OPC_PFX_C2 & OPC_PFX_C2a & OPC_NOP;
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instr_reg <= OPC_PFX_C & OPC_PFX_C2 & OPC_PFX_C2a & OPC_NOP;
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src1_reg <= (others => '0');
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src1_reg <= (others => '0');
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src2_reg <= (others => '0');
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src2_reg <= (others => '0');
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elsif clock'event and clock = '1' then -- rising clock edge
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elsif clock'event and clock = '1' then -- rising clock edge
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if hold = '0' then
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if hold = '0' then
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if stall = '1' then
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if stall = '1' then
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pc_reg <= (others => '0');
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pc_reg <= (others => '0');
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dest_reg <= (others => '0');
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dest_reg <= (others => '0');
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instr_reg <= OPC_PFX_C & OPC_PFX_C2 & OPC_PFX_C2a & OPC_NOP;
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instr_reg <= OPC_PFX_C & OPC_PFX_C2 & OPC_PFX_C2a & OPC_NOP;
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src1_reg <= (others => '0');
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src1_reg <= (others => '0');
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src2_reg <= (others => '0');
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src2_reg <= (others => '0');
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else
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else
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pc_reg <= pc_in;
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pc_reg <= pc_in;
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dest_reg <= dest_in;
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dest_reg <= dest_in;
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instr_reg <= instr;
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instr_reg <= instr;
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src1_reg <= src1_in;
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src1_reg <= src1_in;
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src2_reg <= src2_in;
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src2_reg <= src2_in;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process syn_proc;
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end process syn_proc;
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feedthrough: process (pc_reg, src1_reg, src2_reg)
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feedthrough: process (pc_reg, src1_reg, src2_reg)
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begin -- process feedthrough
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begin -- process feedthrough
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pc_out <= pc_reg;
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pc_out <= pc_reg;
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src1_out <= src1_reg;
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src1_out <= src1_reg;
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src2_out <= src2_reg;
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src2_out <= src2_reg;
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end process feedthrough;
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end process feedthrough;
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do_decode: process (instr_reg, src1_reg, src2_reg, dest_reg)
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do_decode: process (instr_reg, src1_reg, src2_reg, dest_reg)
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begin -- process
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begin -- process
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-- all unknown opcodes trigger interrupt EXC_ERR
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-- all unknown opcodes trigger interrupt EXC_ERR
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imm <= std_logic_vector(to_unsigned(EXC_ERR, REG_WIDTH));
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imm <= std_logic_vector(to_unsigned(EXC_ERR, REG_WIDTH));
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dest_out <= dest_reg;
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dest_out <= dest_reg;
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aop <= ALU_INTR;
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aop <= ALU_INTR;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_INTR;
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iop <= INTR_INTR;
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unit <= UNIT_INTR;
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unit <= UNIT_INTR;
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target <= TARGET_PC;
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target <= TARGET_PC;
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case instr_reg(PDATA_WIDTH-1 downto PDATA_WIDTH-4) is
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case instr_reg(PDATA_WIDTH-1 downto PDATA_WIDTH-4) is
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when
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when
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OPC_ADD => aop <= ALU_ADD;
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OPC_ADD => aop <= ALU_ADD;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
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iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= dest_reg;
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dest_out <= dest_reg;
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when
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when
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OPC_SUB => aop <= ALU_SUB;
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OPC_SUB => aop <= ALU_SUB;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
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iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= dest_reg;
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dest_out <= dest_reg;
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when
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when
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OPC_ADDC => aop <= ALU_ADDC;
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OPC_ADDC => aop <= ALU_ADDC;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
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iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= dest_reg;
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dest_out <= dest_reg;
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when
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when
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OPC_SUBC => aop <= ALU_SUBC;
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OPC_SUBC => aop <= ALU_SUBC;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
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iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= dest_reg;
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dest_out <= dest_reg;
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when
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when
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OPC_AND => aop <= ALU_AND;
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OPC_AND => aop <= ALU_AND;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
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iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= dest_reg;
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dest_out <= dest_reg;
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when
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when
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OPC_OR => aop <= ALU_OR;
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OPC_OR => aop <= ALU_OR;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
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iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= dest_reg;
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dest_out <= dest_reg;
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when
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when
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OPC_XOR => aop <= ALU_XOR;
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OPC_XOR => aop <= ALU_XOR;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
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iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= dest_reg;
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dest_out <= dest_reg;
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when
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when
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OPC_MUL => aop <= ALU_MUL;
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OPC_MUL => aop <= ALU_MUL;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
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iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= dest_reg;
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dest_out <= dest_reg;
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when
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when
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OPC_DIV => aop <= ALU_DIV;
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OPC_DIV => aop <= ALU_DIV;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
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iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= dest_reg;
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dest_out <= dest_reg;
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when
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when
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OPC_UDIV => aop <= ALU_UDIV;
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OPC_UDIV => aop <= ALU_UDIV;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
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iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= dest_reg;
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dest_out <= dest_reg;
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when
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when
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OPC_LDIL => imm <= std_logic_vector(resize(signed(dest_reg & src2_reg), REG_WIDTH));
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OPC_LDIL => imm <= std_logic_vector(resize(signed(dest_reg & src2_reg), REG_WIDTH));
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aop <= ALU_LDIL;
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aop <= ALU_LDIL;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
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iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= src1_reg;
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dest_out <= src1_reg;
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when
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when
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OPC_LDIH => imm <= std_logic_vector(resize(signed(dest_reg & src2_reg), REG_WIDTH));
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OPC_LDIH => imm <= std_logic_vector(resize(signed(dest_reg & src2_reg), REG_WIDTH));
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aop <= ALU_LDIH;
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aop <= ALU_LDIH;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
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iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= src1_reg;
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dest_out <= src1_reg;
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when
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when
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OPC_LDIB => imm <= std_logic_vector(resize(signed(dest_reg & src2_reg), REG_WIDTH));
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OPC_LDIB => imm <= std_logic_vector(resize(signed(dest_reg & src2_reg), REG_WIDTH));
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aop <= ALU_LDIB;
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aop <= ALU_LDIB;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
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iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= src1_reg;
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dest_out <= src1_reg;
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|
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when
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when
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OPC_PFX_A =>
|
OPC_PFX_A =>
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case instr_reg(PDATA_WIDTH-5 downto PDATA_WIDTH-8) is
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case instr_reg(PDATA_WIDTH-5 downto PDATA_WIDTH-8) is
|
when
|
when
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OPC_MOV => aop <= ALU_MOV;
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OPC_MOV => aop <= ALU_MOV;
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mop <= MEM_NOP;
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mop <= MEM_NOP;
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iop <= INTR_NOP;
|
iop <= INTR_NOP;
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unit <= UNIT_ALU;
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unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
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target <= TARGET_REGISTER;
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dest_out <= src1_reg;
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dest_out <= src1_reg;
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when
|
when
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OPC_MOD => aop <= ALU_MOD;
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OPC_MOD => aop <= ALU_MOD;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
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target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_UMOD => aop <= ALU_UMOD;
|
OPC_UMOD => aop <= ALU_UMOD;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_NOT => aop <= ALU_NOT;
|
OPC_NOT => aop <= ALU_NOT;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_NEG => aop <= ALU_NEG;
|
OPC_NEG => aop <= ALU_NEG;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_CMP => aop <= ALU_SUB; -- it's the same
|
OPC_CMP => aop <= ALU_SUB; -- it's the same
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_ADDI => imm <= std_logic_vector(resize(signed(src2_reg), REG_WIDTH));
|
OPC_ADDI => imm <= std_logic_vector(resize(signed(src2_reg), REG_WIDTH));
|
aop <= ALU_ADDI;
|
aop <= ALU_ADDI;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_CMPI => imm <= std_logic_vector(resize(signed(src2_reg), REG_WIDTH));
|
OPC_CMPI => imm <= std_logic_vector(resize(signed(src2_reg), REG_WIDTH));
|
aop <= ALU_CMPI;
|
aop <= ALU_CMPI;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_SHL => aop <= ALU_SHL;
|
OPC_SHL => aop <= ALU_SHL;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_SHR => aop <= ALU_SHR;
|
OPC_SHR => aop <= ALU_SHR;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_SAR => aop <= ALU_SAR;
|
OPC_SAR => aop <= ALU_SAR;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_ROLC => aop <= ALU_ROLC;
|
OPC_ROLC => aop <= ALU_ROLC;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_RORC => aop <= ALU_RORC;
|
OPC_RORC => aop <= ALU_RORC;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_BSET => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
OPC_BSET => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
aop <= ALU_BSET;
|
aop <= ALU_BSET;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_BCLR => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
OPC_BCLR => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
aop <= ALU_BCLR;
|
aop <= ALU_BCLR;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_BTEST => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
OPC_BTEST => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
aop <= ALU_BTEST;
|
aop <= ALU_BTEST;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
when OPC_PFX_B =>
|
when OPC_PFX_B =>
|
case instr_reg(PDATA_WIDTH-5 downto PDATA_WIDTH-8) is
|
case instr_reg(PDATA_WIDTH-5 downto PDATA_WIDTH-8) is
|
when
|
when
|
OPC_LOAD => mop <= MEM_LOAD;
|
OPC_LOAD => mop <= MEM_LOAD;
|
aop <= ALU_NOP;
|
aop <= ALU_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_MEM;
|
unit <= UNIT_MEM;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_LOADL => mop <= MEM_LOADL;
|
OPC_LOADL => mop <= MEM_LOADL;
|
aop <= ALU_NOP;
|
aop <= ALU_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_MEM;
|
unit <= UNIT_MEM;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_LOADH => mop <= MEM_LOADH;
|
OPC_LOADH => mop <= MEM_LOADH;
|
aop <= ALU_NOP;
|
aop <= ALU_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_MEM;
|
unit <= UNIT_MEM;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_LOADB => mop <= MEM_LOADB;
|
OPC_LOADB => mop <= MEM_LOADB;
|
aop <= ALU_NOP;
|
aop <= ALU_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_MEM;
|
unit <= UNIT_MEM;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_STORE => mop <= MEM_STORE;
|
OPC_STORE => mop <= MEM_STORE;
|
aop <= ALU_NOP;
|
aop <= ALU_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_MEM;
|
unit <= UNIT_MEM;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_STOREL => mop <= MEM_STOREL;
|
OPC_STOREL => mop <= MEM_STOREL;
|
aop <= ALU_NOP;
|
aop <= ALU_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_MEM;
|
unit <= UNIT_MEM;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_STOREH => mop <= MEM_STOREH;
|
OPC_STOREH => mop <= MEM_STOREH;
|
aop <= ALU_NOP;
|
aop <= ALU_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_MEM;
|
unit <= UNIT_MEM;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_CALL => aop <= ALU_JMP; -- force alu_pcchg
|
OPC_CALL => aop <= ALU_JMP; -- force alu_pcchg
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_CALL;
|
unit <= UNIT_CALL;
|
target <= TARGET_BOTH;
|
target <= TARGET_BOTH;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
when OPC_PFX_C =>
|
when OPC_PFX_C =>
|
case instr_reg(PDATA_WIDTH-5 downto PDATA_WIDTH-8) is
|
case instr_reg(PDATA_WIDTH-5 downto PDATA_WIDTH-8) is
|
when
|
when
|
OPC_BR => aop <= ALU_NOP;
|
OPC_BR => aop <= ALU_NOP;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_BRZ => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
OPC_BRZ => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
aop <= ALU_BRZ;
|
aop <= ALU_BRZ;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_BRNZ => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
OPC_BRNZ => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
aop <= ALU_BRNZ;
|
aop <= ALU_BRNZ;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_BRLE => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
OPC_BRLE => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
aop <= ALU_BRLE;
|
aop <= ALU_BRLE;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_BRLT => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
OPC_BRLT => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
aop <= ALU_BRLT;
|
aop <= ALU_BRLT;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_BRGE => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
OPC_BRGE => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
aop <= ALU_BRGE;
|
aop <= ALU_BRGE;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_BRGT => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
OPC_BRGT => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
aop <= ALU_BRGT;
|
aop <= ALU_BRGT;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_BRULE => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
OPC_BRULE => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
aop <= ALU_BRULE;
|
aop <= ALU_BRULE;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_BRULT => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
OPC_BRULT => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
aop <= ALU_BRULT;
|
aop <= ALU_BRULT;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_BRUGE => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
OPC_BRUGE => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
aop <= ALU_BRUGE;
|
aop <= ALU_BRUGE;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_BRUGT => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
OPC_BRUGT => imm <= std_logic_vector(resize(signed(src2_reg & src1_reg), REG_WIDTH));
|
aop <= ALU_BRUGT;
|
aop <= ALU_BRUGT;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_SEXT => aop <= ALU_SEXT;
|
OPC_SEXT => aop <= ALU_SEXT;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_LDVEC => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
OPC_LDVEC => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
iop <= INTR_LDVEC;
|
iop <= INTR_LDVEC;
|
aop <= ALU_NOP;
|
aop <= ALU_NOP;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
unit <= UNIT_INTR;
|
unit <= UNIT_INTR;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_STVEC => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
OPC_STVEC => imm <= std_logic_vector(resize(unsigned(src2_reg), REG_WIDTH));
|
iop <= INTR_STVEC;
|
iop <= INTR_STVEC;
|
aop <= ALU_NOP;
|
aop <= ALU_NOP;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
unit <= UNIT_INTR;
|
unit <= UNIT_INTR;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_PFX_C1 =>
|
OPC_PFX_C1 =>
|
case instr_reg(PDATA_WIDTH-9 downto PDATA_WIDTH-12) is
|
case instr_reg(PDATA_WIDTH-9 downto PDATA_WIDTH-12) is
|
when
|
when
|
OPC_JMP => aop <= ALU_JMP;
|
OPC_JMP => aop <= ALU_JMP;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_JMPZ => aop <= ALU_JMPZ;
|
OPC_JMPZ => aop <= ALU_JMPZ;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_JMPNZ => aop <= ALU_JMPNZ;
|
OPC_JMPNZ => aop <= ALU_JMPNZ;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_JMPLE => aop <= ALU_JMPLE;
|
OPC_JMPLE => aop <= ALU_JMPLE;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_JMPLT => aop <= ALU_JMPLT;
|
OPC_JMPLT => aop <= ALU_JMPLT;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_JMPGE => aop <= ALU_JMPGE;
|
OPC_JMPGE => aop <= ALU_JMPGE;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_JMPGT => aop <= ALU_JMPGT;
|
OPC_JMPGT => aop <= ALU_JMPGT;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_JMPULE => aop <= ALU_JMPULE;
|
OPC_JMPULE => aop <= ALU_JMPULE;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_JMPULT => aop <= ALU_JMPULT;
|
OPC_JMPULT => aop <= ALU_JMPULT;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_JMPUGE => aop <= ALU_JMPUGE;
|
OPC_JMPUGE => aop <= ALU_JMPUGE;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_JMPUGT => aop <= ALU_JMPUGT;
|
OPC_JMPUGT => aop <= ALU_JMPUGT;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_INTR => imm <= std_logic_vector(resize(unsigned(src1_reg), REG_WIDTH));
|
OPC_INTR => imm <= std_logic_vector(resize(unsigned(src1_reg), REG_WIDTH));
|
aop <= ALU_INTR;
|
aop <= ALU_INTR;
|
iop <= INTR_INTR;
|
iop <= INTR_INTR;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
unit <= UNIT_INTR;
|
unit <= UNIT_INTR;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_GETFL => aop <= ALU_GETFL;
|
OPC_GETFL => aop <= ALU_GETFL;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_SETFL => aop <= ALU_SETFL;
|
OPC_SETFL => aop <= ALU_SETFL;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_GETIRA => iop <= INTR_GETIRA;
|
OPC_GETIRA => iop <= INTR_GETIRA;
|
aop <= ALU_NOP;
|
aop <= ALU_NOP;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
unit <= UNIT_INTR;
|
unit <= UNIT_INTR;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
|
|
when
|
when
|
OPC_SETIRA => iop <= INTR_SETIRA;
|
OPC_SETIRA => iop <= INTR_SETIRA;
|
aop <= ALU_NOP;
|
aop <= ALU_NOP;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
unit <= UNIT_INTR;
|
unit <= UNIT_INTR;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
when
|
when
|
OPC_PFX_C2 =>
|
OPC_PFX_C2 =>
|
case instr_reg(PDATA_WIDTH-9 downto PDATA_WIDTH-12) is
|
case instr_reg(PDATA_WIDTH-9 downto PDATA_WIDTH-12) is
|
when
|
when
|
OPC_GETSHFL => aop <= ALU_GETSHFL;
|
OPC_GETSHFL => aop <= ALU_GETSHFL;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_REGISTER;
|
target <= TARGET_REGISTER;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_SETSHFL => aop <= ALU_SETSHFL;
|
OPC_SETSHFL => aop <= ALU_SETSHFL;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_PFX_C2a =>
|
OPC_PFX_C2a =>
|
case instr_reg(PDATA_WIDTH-13 downto PDATA_WIDTH-16) is
|
case instr_reg(PDATA_WIDTH-13 downto PDATA_WIDTH-16) is
|
when
|
when
|
OPC_RETI => aop <= ALU_RETI;
|
OPC_RETI => aop <= ALU_RETI;
|
iop <= INTR_RETI;
|
iop <= INTR_RETI;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
unit <= UNIT_INTR;
|
unit <= UNIT_INTR;
|
target <= TARGET_PC;
|
target <= TARGET_PC;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_NOP => aop <= ALU_NOP;
|
OPC_NOP => aop <= ALU_NOP;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_SEI => aop <= ALU_SEI;
|
OPC_SEI => aop <= ALU_SEI;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when
|
when
|
OPC_CLI => aop <= ALU_CLI;
|
OPC_CLI => aop <= ALU_CLI;
|
mop <= MEM_NOP;
|
mop <= MEM_NOP;
|
iop <= INTR_NOP;
|
iop <= INTR_NOP;
|
unit <= UNIT_ALU;
|
unit <= UNIT_ALU;
|
target <= TARGET_NONE;
|
target <= TARGET_NONE;
|
dest_out <= src1_reg;
|
dest_out <= src1_reg;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
end process;
|
end process;
|
|
|
end behaviour;
|
end behaviour;
|
|
|