-- This file is part of the marca processor.
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-- This file is part of the marca processor.
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- This program is free software; you can redistribute it and/or modify it
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-- This program is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU Library General Public License as published
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-- under the terms of the GNU Library General Public License as published
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- any later version.
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-- any later version.
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Library General Public License for more details.
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-- Library General Public License for more details.
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-- You should have received a copy of the GNU Library General Public
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-- You should have received a copy of the GNU Library General Public
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-- License along with this program; if not, write to the Free Software
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-- License along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- MARCA execution stage
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-- MARCA execution stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- entity for the execution pipeline stage
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-- entity for the execution pipeline stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Wolfgang Puffitsch
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-- Wolfgang Puffitsch
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-- Computer Architecture Lab, Group 3
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-- Computer Architecture Lab, Group 3
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use work.marca_pkg.all;
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use work.marca_pkg.all;
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entity execute is
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entity execute is
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port (
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port (
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clock : in std_logic;
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clock : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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busy : out std_logic;
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busy : out std_logic;
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stall : in std_logic;
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stall : in std_logic;
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pc_in : in std_logic_vector(REG_WIDTH-1 downto 0);
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pc_in : in std_logic_vector(REG_WIDTH-1 downto 0);
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pcchg : out std_logic;
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pcchg : out std_logic;
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pc_out : out std_logic_vector(REG_WIDTH-1 downto 0);
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pc_out : out std_logic_vector(REG_WIDTH-1 downto 0);
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dest_in : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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dest_in : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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dest_out : out std_logic_vector(REG_COUNT_LOG-1 downto 0);
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dest_out : out std_logic_vector(REG_COUNT_LOG-1 downto 0);
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src1 : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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src1 : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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src2 : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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src2 : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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aop : in ALU_OP;
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aop : in ALU_OP;
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mop : in MEM_OP;
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mop : in MEM_OP;
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iop : in INTR_OP;
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iop : in INTR_OP;
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op1 : in std_logic_vector(REG_WIDTH-1 downto 0);
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op1 : in std_logic_vector(REG_WIDTH-1 downto 0);
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op2 : in std_logic_vector(REG_WIDTH-1 downto 0);
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op2 : in std_logic_vector(REG_WIDTH-1 downto 0);
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imm : in std_logic_vector(REG_WIDTH-1 downto 0);
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imm : in std_logic_vector(REG_WIDTH-1 downto 0);
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unit : in UNIT_SELECTOR;
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unit : in UNIT_SELECTOR;
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target_in : in TARGET_SELECTOR;
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target_in : in TARGET_SELECTOR;
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target_out : out TARGET_SELECTOR;
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target_out : out TARGET_SELECTOR;
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result : out std_logic_vector(REG_WIDTH-1 downto 0);
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result : out std_logic_vector(REG_WIDTH-1 downto 0);
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fw_ena : in std_logic;
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fw_ena : in std_logic;
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fw_dest : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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fw_dest : in std_logic_vector(REG_COUNT_LOG-1 downto 0);
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fw_val : in std_logic_vector(REG_WIDTH-1 downto 0);
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fw_val : in std_logic_vector(REG_WIDTH-1 downto 0);
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ext_in : in std_logic_vector(IN_BITS-1 downto 0);
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ext_in : in std_logic_vector(IN_BITS-1 downto 0);
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ext_out : out std_logic_vector(OUT_BITS-1 downto 0));
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ext_out : out std_logic_vector(OUT_BITS-1 downto 0));
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end execute;
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end execute;
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