--
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--
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-- fifo.vhd
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-- fifo.vhd
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--
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--
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-- simple fifo
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-- simple fifo
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--
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--
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-- uses FF and every rd or wr has to 'bubble' through the hole fifo.
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-- uses FF and every rd or wr has to 'bubble' through the hole fifo.
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--
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--
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-- Author: Martin Schoeberl martin.schoeberl@chello.at
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-- Author: Martin Schoeberl martin.schoeberl@chello.at
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--
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--
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--
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--
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-- resources on ACEX1K
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-- resources on ACEX1K
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--
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--
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-- (width+2)*depth-1 LCs
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-- (width+2)*depth-1 LCs
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--
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--
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--
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--
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-- 2002-01-06 first working version
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-- 2002-01-06 first working version
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-- 2002-11-03 a signal for reaching threshold
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-- 2002-11-03 a signal for reaching threshold
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-- 2005-02-20 change entity order for modelsim vcom
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-- 2005-02-20 change entity order for modelsim vcom
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.marca_pkg.all;
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use work.marca_pkg.all;
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entity fifo_elem is
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entity fifo_elem is
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generic (width : integer);
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generic (width : integer);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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din : in std_logic_vector(width-1 downto 0);
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din : in std_logic_vector(width-1 downto 0);
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dout : out std_logic_vector(width-1 downto 0);
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dout : out std_logic_vector(width-1 downto 0);
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rd : in std_logic;
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rd : in std_logic;
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wr : in std_logic;
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wr : in std_logic;
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rd_prev : out std_logic;
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rd_prev : out std_logic;
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full : out std_logic
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full : out std_logic
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);
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);
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end fifo_elem;
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end fifo_elem;
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architecture rtl of fifo_elem is
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architecture rtl of fifo_elem is
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signal buf : std_logic_vector(width-1 downto 0);
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signal buf : std_logic_vector(width-1 downto 0);
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signal f : std_logic;
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signal f : std_logic;
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begin
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begin
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dout <= buf;
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dout <= buf;
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process(clk, reset, f)
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process(clk, reset, f)
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begin
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begin
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full <= f;
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full <= f;
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if reset = RESET_ACTIVE then
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if reset = RESET_ACTIVE then
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buf <= (others => '0');
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buf <= (others => '0');
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f <= '0';
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f <= '0';
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rd_prev <= '0';
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rd_prev <= '0';
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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rd_prev <= '0';
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rd_prev <= '0';
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if f='0' then
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if f='0' then
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if wr='1' then
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if wr='1' then
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rd_prev <= '1';
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rd_prev <= '1';
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buf <= din;
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buf <= din;
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f <= '1';
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f <= '1';
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end if;
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end if;
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else
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else
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if rd='1' then
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if rd='1' then
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f <= '0';
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f <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end rtl;
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end rtl;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity fifo is
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entity fifo is
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generic (width : integer := 8; depth : integer := 4; thres : integer := 2);
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generic (width : integer := 8; depth : integer := 4; thres : integer := 2);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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din : in std_logic_vector(width-1 downto 0);
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din : in std_logic_vector(width-1 downto 0);
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dout : out std_logic_vector(width-1 downto 0);
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dout : out std_logic_vector(width-1 downto 0);
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rd : in std_logic;
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rd : in std_logic;
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wr : in std_logic;
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wr : in std_logic;
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empty : out std_logic;
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empty : out std_logic;
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full : out std_logic;
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full : out std_logic;
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half : out std_logic
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half : out std_logic
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);
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);
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end fifo ;
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end fifo ;
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architecture rtl of fifo is
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architecture rtl of fifo is
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component fifo_elem is
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component fifo_elem is
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generic (width : integer);
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generic (width : integer);
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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din : in std_logic_vector(width-1 downto 0);
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din : in std_logic_vector(width-1 downto 0);
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dout : out std_logic_vector(width-1 downto 0);
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dout : out std_logic_vector(width-1 downto 0);
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rd : in std_logic;
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rd : in std_logic;
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wr : in std_logic;
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wr : in std_logic;
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rd_prev : out std_logic;
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rd_prev : out std_logic;
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full : out std_logic);
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full : out std_logic);
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end component;
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end component;
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signal r, w, rp, f : std_logic_vector(depth-1 downto 0);
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signal r, w, rp, f : std_logic_vector(depth-1 downto 0);
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type d_array is array (0 to depth-1) of std_logic_vector(width-1 downto 0);
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type d_array is array (0 to depth-1) of std_logic_vector(width-1 downto 0);
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signal di, do : d_array;
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signal di, do : d_array;
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begin
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begin
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g1: for i in 0 to depth-1 generate
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g1: for i in 0 to depth-1 generate
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f1: fifo_elem generic map (width)
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f1: fifo_elem generic map (width)
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port map (clk, reset, di(i), do(i), r(i), w(i), rp(i), f(i));
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port map (clk, reset, di(i), do(i), r(i), w(i), rp(i), f(i));
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x: if i<depth-1 generate
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x: if i<depth-1 generate
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r(i) <= rp(i+1);
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r(i) <= rp(i+1);
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w(i+1) <= f(i);
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w(i+1) <= f(i);
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di(i+1) <= do(i);
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di(i+1) <= do(i);
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end generate;
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end generate;
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end generate;
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end generate;
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di(0) <= din;
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di(0) <= din;
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dout <= do(depth-1);
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dout <= do(depth-1);
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w(0) <= wr;
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w(0) <= wr;
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r(depth-1) <= rd;
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r(depth-1) <= rd;
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full <= f(0);
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full <= f(0);
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half <= f(depth-thres);
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half <= f(depth-thres);
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empty <= not f(depth-1);
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empty <= not f(depth-1);
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end rtl;
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end rtl;
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