-- This file is part of the marca processor.
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-- This file is part of the marca processor.
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- This program is free software; you can redistribute it and/or modify it
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-- This program is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU Library General Public License as published
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-- under the terms of the GNU Library General Public License as published
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- any later version.
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-- any later version.
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Library General Public License for more details.
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-- Library General Public License for more details.
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-- You should have received a copy of the GNU Library General Public
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-- You should have received a copy of the GNU Library General Public
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-- License along with this program; if not, write to the Free Software
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-- License along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- MARCA interrupt unit
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-- MARCA interrupt unit
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- architecture for the interrupt unit
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-- architecture for the interrupt unit
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Wolfgang Puffitsch
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-- Wolfgang Puffitsch
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-- Computer Architecture Lab, Group 3
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-- Computer Architecture Lab, Group 3
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.marca_pkg.all;
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use work.marca_pkg.all;
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architecture behaviour of intr is
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architecture behaviour of intr is
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type vectors is array (VEC_COUNT-1 downto 0) of std_logic_vector(REG_WIDTH-1 downto 0);
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type vectors is array (VEC_COUNT-1 downto 0) of std_logic_vector(REG_WIDTH-1 downto 0);
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signal vecs, next_vecs : vectors;
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signal vecs, next_vecs : vectors;
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signal ira, next_ira : std_logic_vector(REG_WIDTH-1 downto 0);
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signal ira, next_ira : std_logic_vector(REG_WIDTH-1 downto 0);
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begin -- behaviour
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begin -- behaviour
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syn_proc: process (clock, reset)
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syn_proc: process (clock, reset)
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begin -- process syn_proc
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begin -- process syn_proc
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if reset = RESET_ACTIVE then -- asynchronous reset (active low)
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if reset = RESET_ACTIVE then -- asynchronous reset (active low)
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vecs <= (others => (others => '0'));
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vecs <= (others => (others => '0'));
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ira <= (others => '0');
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ira <= (others => '0');
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elsif clock'event and clock = '1' then -- rising clock edge
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elsif clock'event and clock = '1' then -- rising clock edge
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vecs <= next_vecs;
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vecs <= next_vecs;
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ira <= next_ira;
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ira <= next_ira;
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end if;
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end if;
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end process syn_proc;
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end process syn_proc;
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compute: process (op, a, i, pc, vecs, ira, enable, trigger)
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compute: process (op, a, i, pc, vecs, ira, enable, trigger)
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begin -- process compute
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begin -- process compute
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next_vecs <= vecs;
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next_vecs <= vecs;
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next_ira <= ira;
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next_ira <= ira;
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exc <= '0';
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exc <= '0';
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pcchg <= '0';
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pcchg <= '0';
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result <= (others => '0');
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result <= (others => '0');
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case op is
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case op is
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when INTR_INTR =>
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when INTR_INTR =>
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if enable = '1' then
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if enable = '1' then
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pcchg <= '1';
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pcchg <= '1';
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result <= vecs(to_integer(unsigned(i)));
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result <= vecs(to_integer(unsigned(i)));
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next_ira <= std_logic_vector(unsigned(pc) + 1);
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next_ira <= std_logic_vector(unsigned(pc) + 1);
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end if;
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end if;
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when INTR_RETI =>
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when INTR_RETI =>
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pcchg <= '1';
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pcchg <= '1';
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result <= ira;
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result <= ira;
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when INTR_SETIRA =>
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when INTR_SETIRA =>
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next_ira <= a;
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next_ira <= a;
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when INTR_GETIRA =>
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when INTR_GETIRA =>
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result <= ira;
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result <= ira;
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when INTR_STVEC =>
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when INTR_STVEC =>
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next_vecs(to_integer(unsigned(i))) <= a;
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next_vecs(to_integer(unsigned(i))) <= a;
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when INTR_LDVEC =>
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when INTR_LDVEC =>
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result <= vecs(to_integer(unsigned(i)));
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result <= vecs(to_integer(unsigned(i)));
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when others => null;
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when others => null;
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end case;
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end case;
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if enable = '1' then
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if enable = '1' then
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for v in VEC_COUNT-1 downto 1 loop
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for v in VEC_COUNT-1 downto 1 loop
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if trigger(v) = '1' then
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if trigger(v) = '1' then
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exc <= '1';
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exc <= '1';
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pcchg <= '1';
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pcchg <= '1';
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result <= vecs(v);
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result <= vecs(v);
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if v = EXC_ALU or v = EXC_MEM then
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if v = EXC_ALU or v = EXC_MEM then
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-- don't repeat division by zero and ill memory access
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-- don't repeat division by zero and ill memory access
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next_ira <= std_logic_vector(unsigned(pc) + 1);
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next_ira <= std_logic_vector(unsigned(pc) + 1);
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else
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else
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-- repeat the instruction if interrupted
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-- repeat the instruction if interrupted
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next_ira <= pc;
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next_ira <= pc;
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end if;
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end if;
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end if;
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end if;
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end loop;
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end loop;
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end if;
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end if;
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end process compute;
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end process compute;
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end behaviour;
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end behaviour;
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