-- This file is part of the marca processor.
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-- This file is part of the marca processor.
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- This program is free software; you can redistribute it and/or modify it
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-- This program is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU Library General Public License as published
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-- under the terms of the GNU Library General Public License as published
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- any later version.
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-- any later version.
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|
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Library General Public License for more details.
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-- Library General Public License for more details.
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-- You should have received a copy of the GNU Library General Public
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-- You should have received a copy of the GNU Library General Public
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-- License along with this program; if not, write to the Free Software
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-- License along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- MARCA fetch stage
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-- MARCA fetch stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- architecture for the instruction-fetch pipeline stage
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-- architecture for the instruction-fetch pipeline stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Wolfgang Puffitsch
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-- Wolfgang Puffitsch
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-- Computer Architecture Lab, Group 3
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-- Computer Architecture Lab, Group 3
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.marca_pkg.all;
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use work.marca_pkg.all;
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use work.sc_pkg.all;
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use work.sc_pkg.all;
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architecture behaviour of mem is
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architecture behaviour of mem is
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type WAIT_STATE is (WAIT_LOAD_EVEN, WAIT_LOAD_ODD,
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type WAIT_STATE is (WAIT_LOAD_EVEN, WAIT_LOAD_ODD,
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WAIT_LOADL_EVEN, WAIT_LOADL_ODD,
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WAIT_LOADL_EVEN, WAIT_LOADL_ODD,
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WAIT_LOADH_EVEN, WAIT_LOADH_ODD,
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WAIT_LOADH_EVEN, WAIT_LOADH_ODD,
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WAIT_LOADB_EVEN, WAIT_LOADB_ODD,
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WAIT_LOADB_EVEN, WAIT_LOADB_ODD,
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WAIT_STORE,
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WAIT_STORE,
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WAIT_NONE);
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WAIT_NONE);
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signal state : WAIT_STATE;
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signal state : WAIT_STATE;
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signal next_state : WAIT_STATE;
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signal next_state : WAIT_STATE;
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|
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signal old_data : std_logic_vector(REG_WIDTH-1 downto 0);
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signal old_data : std_logic_vector(REG_WIDTH-1 downto 0);
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signal next_data : std_logic_vector(REG_WIDTH-1 downto 0);
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signal next_data : std_logic_vector(REG_WIDTH-1 downto 0);
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component data_memory
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component data_memory
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port (
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port (
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clken : in std_logic;
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clken : in std_logic;
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clock : in std_logic;
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clock : in std_logic;
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wren : in std_logic;
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wren : in std_logic;
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address : in std_logic_vector (ADDR_WIDTH-2 downto 0);
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address : in std_logic_vector (ADDR_WIDTH-2 downto 0);
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data : in std_logic_vector (DATA_WIDTH-1 downto 0);
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data : in std_logic_vector (DATA_WIDTH-1 downto 0);
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q : out std_logic_vector (DATA_WIDTH-1 downto 0));
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q : out std_logic_vector (DATA_WIDTH-1 downto 0));
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end component;
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end component;
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signal ram_enable : std_logic;
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signal ram_enable : std_logic;
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signal wren0 : std_logic;
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signal wren0 : std_logic;
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signal a0 : std_logic_vector(ADDR_WIDTH-2 downto 0);
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signal a0 : std_logic_vector(ADDR_WIDTH-2 downto 0);
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signal d0 : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal d0 : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal q0 : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal q0 : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal wren1 : std_logic;
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signal wren1 : std_logic;
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signal a1 : std_logic_vector(ADDR_WIDTH-2 downto 0);
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signal a1 : std_logic_vector(ADDR_WIDTH-2 downto 0);
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signal d1 : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal d1 : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal q1 : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal q1 : std_logic_vector(DATA_WIDTH-1 downto 0);
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component data_rom
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component data_rom
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generic (
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generic (
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init_file : string);
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init_file : string);
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port (
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port (
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clken : in std_logic;
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clken : in std_logic;
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clock : in std_logic;
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clock : in std_logic;
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address : in std_logic_vector (RADDR_WIDTH-2 downto 0);
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address : in std_logic_vector (RADDR_WIDTH-2 downto 0);
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q : out std_logic_vector (RDATA_WIDTH-1 downto 0));
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q : out std_logic_vector (RDATA_WIDTH-1 downto 0));
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end component;
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end component;
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signal rom_enable : std_logic;
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signal rom_enable : std_logic;
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signal ra0 : std_logic_vector(RADDR_WIDTH-2 downto 0);
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signal ra0 : std_logic_vector(RADDR_WIDTH-2 downto 0);
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signal rq0 : std_logic_vector(RDATA_WIDTH-1 downto 0);
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signal rq0 : std_logic_vector(RDATA_WIDTH-1 downto 0);
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signal ra1 : std_logic_vector(RADDR_WIDTH-2 downto 0);
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signal ra1 : std_logic_vector(RADDR_WIDTH-2 downto 0);
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signal rq1 : std_logic_vector(RDATA_WIDTH-1 downto 0);
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signal rq1 : std_logic_vector(RDATA_WIDTH-1 downto 0);
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signal sc_input : SC_IN;
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signal sc_input : SC_IN;
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signal sc_output : SC_OUT;
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signal sc_output : SC_OUT;
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component sc_uart
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component sc_uart
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generic (
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generic (
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clock_freq : integer;
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clock_freq : integer;
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baud_rate : integer;
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baud_rate : integer;
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txf_depth : integer; txf_thres : integer;
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txf_depth : integer; txf_thres : integer;
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rxf_depth : integer; rxf_thres : integer);
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rxf_depth : integer; rxf_thres : integer);
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port (
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port (
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clock : in std_logic;
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clock : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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input : in SC_IN;
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input : in SC_IN;
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output : out SC_OUT;
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output : out SC_OUT;
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intr : out std_logic;
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intr : out std_logic;
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txd : out std_logic;
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txd : out std_logic;
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rxd : in std_logic;
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rxd : in std_logic;
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nrts : out std_logic;
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nrts : out std_logic;
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ncts : in std_logic);
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ncts : in std_logic);
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end component;
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end component;
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signal uart_input : SC_IN;
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signal uart_input : SC_IN;
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signal uart_output : SC_OUT;
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signal uart_output : SC_OUT;
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begin -- behaviour
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begin -- behaviour
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intrs(VEC_COUNT-1 downto 4) <= (others => '0');
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intrs(VEC_COUNT-1 downto 4) <= (others => '0');
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data_memory_0_unit : data_memory
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data_memory_0_unit : data_memory
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port map (
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port map (
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clken => ram_enable,
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clken => ram_enable,
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clock => clock,
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clock => clock,
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wren => wren0,
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wren => wren0,
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address => a0,
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address => a0,
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data => d0,
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data => d0,
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q => q0);
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q => q0);
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data_memory_1_unit : data_memory
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data_memory_1_unit : data_memory
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port map (
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port map (
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clken => ram_enable,
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clken => ram_enable,
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clock => clock,
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clock => clock,
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wren => wren1,
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wren => wren1,
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address => a1,
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address => a1,
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data => d1,
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data => d1,
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q => q1);
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q => q1);
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data_rom_0_unit : data_rom
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data_rom_0_unit : data_rom
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generic map (
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generic map (
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init_file => "../vhdl/rom0.mif")
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init_file => "../vhdl/rom0.mif")
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port map (
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port map (
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clken => rom_enable,
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clken => rom_enable,
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clock => clock,
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clock => clock,
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address => ra0,
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address => ra0,
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q => rq0);
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q => rq0);
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data_rom_1_unit : data_rom
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data_rom_1_unit : data_rom
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generic map (
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generic map (
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init_file => "../vhdl/rom1.mif")
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init_file => "../vhdl/rom1.mif")
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port map (
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port map (
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clken => rom_enable,
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clken => rom_enable,
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clock => clock,
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clock => clock,
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address => ra1,
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address => ra1,
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q => rq1);
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q => rq1);
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uart_unit : sc_uart
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uart_unit : sc_uart
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generic map (
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generic map (
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clock_freq => CLOCK_FREQ,
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clock_freq => CLOCK_FREQ,
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baud_rate => UART_BAUD_RATE,
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baud_rate => UART_BAUD_RATE,
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txf_depth => 2, txf_thres => 1,
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txf_depth => 2, txf_thres => 1,
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rxf_depth => 2, rxf_thres => 1)
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rxf_depth => 2, rxf_thres => 1)
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port map (
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port map (
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clock => clock,
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clock => clock,
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reset => reset,
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reset => reset,
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input => uart_input,
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input => uart_input,
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output => uart_output,
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output => uart_output,
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intr => intrs(UART_INTR),
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intr => intrs(UART_INTR),
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txd => ext_out(UART_TXD),
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txd => ext_out(UART_TXD),
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rxd => ext_in(UART_RXD),
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rxd => ext_in(UART_RXD),
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nrts => ext_out(UART_NRTS),
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nrts => ext_out(UART_NRTS),
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ncts => ext_in(UART_NCTS));
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ncts => ext_in(UART_NCTS));
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syn_proc: process (clock, reset)
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syn_proc: process (clock, reset)
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begin -- process syn_proc
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begin -- process syn_proc
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if reset = RESET_ACTIVE then -- asynchronous reset (active low)
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if reset = RESET_ACTIVE then -- asynchronous reset (active low)
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state <= WAIT_NONE;
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state <= WAIT_NONE;
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old_data <= (others => '0');
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old_data <= (others => '0');
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elsif clock'event and clock = '1' then -- rising clock edge
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elsif clock'event and clock = '1' then -- rising clock edge
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state <= next_state;
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state <= next_state;
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old_data <= next_data;
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old_data <= next_data;
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end if;
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end if;
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end process syn_proc;
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end process syn_proc;
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business: process (next_state)
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business: process (next_state)
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begin -- process business
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begin -- process business
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if next_state /= WAIT_NONE then
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if next_state /= WAIT_NONE then
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busy <= '1';
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busy <= '1';
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else
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else
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busy <= '0';
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busy <= '0';
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end if;
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end if;
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end process business;
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end process business;
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sc_mux: process (address, sc_input,
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sc_mux: process (address, sc_input,
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uart_output)
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uart_output)
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begin -- process sc_mux
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begin -- process sc_mux
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uart_input <= SC_IN_NULL;
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uart_input <= SC_IN_NULL;
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sc_output <= SC_OUT_NULL;
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sc_output <= SC_OUT_NULL;
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case address(REG_WIDTH-1 downto SC_ADDR_WIDTH+1) is
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case address(REG_WIDTH-1 downto SC_ADDR_WIDTH+1) is
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when UART_BASE_ADDR =>
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when UART_BASE_ADDR =>
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uart_input <= sc_input;
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uart_input <= sc_input;
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sc_output <= uart_output;
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sc_output <= uart_output;
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when others => null;
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when others => null;
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end case;
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end case;
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end process sc_mux;
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end process sc_mux;
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readwrite: process (state, op, address, data, old_data, q0, q1, rq0, rq1, sc_output)
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readwrite: process (state, op, address, data, old_data, q0, q1, rq0, rq1, sc_output)
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begin -- process readwrite
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begin -- process readwrite
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exc <= '0';
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exc <= '0';
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ram_enable <= '0';
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ram_enable <= '0';
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wren0 <= '0';
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wren0 <= '0';
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wren1 <= '0';
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wren1 <= '0';
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|
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a0 <= (others => '0');
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a0 <= (others => '0');
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d0 <= (others => '0');
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d0 <= (others => '0');
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|
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a1 <= (others => '0');
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a1 <= (others => '0');
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d1 <= (others => '0');
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d1 <= (others => '0');
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|
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rom_enable <= '0';
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rom_enable <= '0';
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|
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ra0 <= (others => '0');
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ra0 <= (others => '0');
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ra1 <= (others => '0');
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ra1 <= (others => '0');
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|
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sc_input <= SC_IN_NULL;
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sc_input <= SC_IN_NULL;
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|
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result <= (others => '0');
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result <= (others => '0');
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|
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next_state <= WAIT_NONE;
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next_state <= WAIT_NONE;
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next_data <= data;
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next_data <= data;
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|
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if unsigned(address) >= unsigned(MEM_MIN_ADDR)
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if unsigned(address) >= unsigned(MEM_MIN_ADDR)
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and unsigned(address) <= unsigned(MEM_MAX_ADDR) then
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and unsigned(address) <= unsigned(MEM_MAX_ADDR) then
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|
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-- regular memory access
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-- regular memory access
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if op /= MEM_NOP then
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if op /= MEM_NOP then
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ram_enable <= '1';
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ram_enable <= '1';
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end if;
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end if;
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case state is
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case state is
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when WAIT_LOAD_EVEN => result(REG_WIDTH-1 downto REG_WIDTH/2) <= q1;
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when WAIT_LOAD_EVEN => result(REG_WIDTH-1 downto REG_WIDTH/2) <= q1;
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result(REG_WIDTH/2-1 downto 0) <= q0;
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result(REG_WIDTH/2-1 downto 0) <= q0;
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next_state <= WAIT_NONE;
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next_state <= WAIT_NONE;
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|
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when WAIT_LOAD_ODD => result(REG_WIDTH-1 downto REG_WIDTH/2) <= q0;
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when WAIT_LOAD_ODD => result(REG_WIDTH-1 downto REG_WIDTH/2) <= q0;
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result(REG_WIDTH/2-1 downto 0) <= q1;
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result(REG_WIDTH/2-1 downto 0) <= q1;
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next_state <= WAIT_NONE;
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next_state <= WAIT_NONE;
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|
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when WAIT_LOADL_EVEN => result(REG_WIDTH-1 downto REG_WIDTH/2) <= old_data(REG_WIDTH-1 downto REG_WIDTH/2);
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when WAIT_LOADL_EVEN => result(REG_WIDTH-1 downto REG_WIDTH/2) <= old_data(REG_WIDTH-1 downto REG_WIDTH/2);
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result(REG_WIDTH/2-1 downto 0) <= q0;
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result(REG_WIDTH/2-1 downto 0) <= q0;
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next_state <= WAIT_NONE;
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next_state <= WAIT_NONE;
|
|
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when WAIT_LOADL_ODD => result(REG_WIDTH-1 downto REG_WIDTH/2) <= old_data(REG_WIDTH-1 downto REG_WIDTH/2);
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when WAIT_LOADL_ODD => result(REG_WIDTH-1 downto REG_WIDTH/2) <= old_data(REG_WIDTH-1 downto REG_WIDTH/2);
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result(REG_WIDTH/2-1 downto 0) <= q1;
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result(REG_WIDTH/2-1 downto 0) <= q1;
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next_state <= WAIT_NONE;
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next_state <= WAIT_NONE;
|
|
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when WAIT_LOADH_EVEN => result(REG_WIDTH-1 downto REG_WIDTH/2) <= q0;
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when WAIT_LOADH_EVEN => result(REG_WIDTH-1 downto REG_WIDTH/2) <= q0;
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result(REG_WIDTH/2-1 downto 0) <= old_data(REG_WIDTH/2-1 downto 0);
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result(REG_WIDTH/2-1 downto 0) <= old_data(REG_WIDTH/2-1 downto 0);
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next_state <= WAIT_NONE;
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next_state <= WAIT_NONE;
|
|
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when WAIT_LOADH_ODD => result(REG_WIDTH-1 downto REG_WIDTH/2) <= q1;
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when WAIT_LOADH_ODD => result(REG_WIDTH-1 downto REG_WIDTH/2) <= q1;
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result(REG_WIDTH/2-1 downto 0) <= old_data(REG_WIDTH/2-1 downto 0);
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result(REG_WIDTH/2-1 downto 0) <= old_data(REG_WIDTH/2-1 downto 0);
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next_state <= WAIT_NONE;
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next_state <= WAIT_NONE;
|
|
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when WAIT_LOADB_EVEN => result <= std_logic_vector(resize(signed(q0), REG_WIDTH));
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when WAIT_LOADB_EVEN => result <= std_logic_vector(resize(signed(q0), REG_WIDTH));
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next_state <= WAIT_NONE;
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next_state <= WAIT_NONE;
|
|
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when WAIT_LOADB_ODD => result <= std_logic_vector(resize(signed(q1), REG_WIDTH));
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when WAIT_LOADB_ODD => result <= std_logic_vector(resize(signed(q1), REG_WIDTH));
|
next_state <= WAIT_NONE;
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next_state <= WAIT_NONE;
|
|
|
when WAIT_NONE =>
|
when WAIT_NONE =>
|
case op is
|
case op is
|
when MEM_LOAD => if address(0) = '0' then
|
when MEM_LOAD => if address(0) = '0' then
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
a1 <= address(ADDR_WIDTH-1 downto 1);
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next_state <= WAIT_LOAD_EVEN;
|
next_state <= WAIT_LOAD_EVEN;
|
else
|
else
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
a0 <= std_logic_vector(unsigned(address(ADDR_WIDTH-1 downto 1)) + 1);
|
a0 <= std_logic_vector(unsigned(address(ADDR_WIDTH-1 downto 1)) + 1);
|
next_state <= WAIT_LOAD_ODD;
|
next_state <= WAIT_LOAD_ODD;
|
end if;
|
end if;
|
when MEM_LOADL => if address(0) = '0' then
|
when MEM_LOADL => if address(0) = '0' then
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
next_state <= WAIT_LOADL_EVEN;
|
next_state <= WAIT_LOADL_EVEN;
|
else
|
else
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
next_state <= WAIT_LOADL_ODD;
|
next_state <= WAIT_LOADL_ODD;
|
end if;
|
end if;
|
when MEM_LOADH => if address(0) = '0' then
|
when MEM_LOADH => if address(0) = '0' then
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
next_state <= WAIT_LOADH_EVEN;
|
next_state <= WAIT_LOADH_EVEN;
|
else
|
else
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
next_state <= WAIT_LOADH_ODD;
|
next_state <= WAIT_LOADH_ODD;
|
end if;
|
end if;
|
when MEM_LOADB => if address(0) = '0' then
|
when MEM_LOADB => if address(0) = '0' then
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
next_state <= WAIT_LOADB_EVEN;
|
next_state <= WAIT_LOADB_EVEN;
|
else
|
else
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
next_state <= WAIT_LOADB_ODD;
|
next_state <= WAIT_LOADB_ODD;
|
end if;
|
end if;
|
when MEM_STORE => if address(0) = '0' then
|
when MEM_STORE => if address(0) = '0' then
|
wren0 <= '1';
|
wren0 <= '1';
|
wren1 <= '1';
|
wren1 <= '1';
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
d0 <= data(REG_WIDTH/2-1 downto 0);
|
d0 <= data(REG_WIDTH/2-1 downto 0);
|
d1 <= data(REG_WIDTH-1 downto REG_WIDTH/2);
|
d1 <= data(REG_WIDTH-1 downto REG_WIDTH/2);
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
else
|
else
|
wren0 <= '1';
|
wren0 <= '1';
|
wren1 <= '1';
|
wren1 <= '1';
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
a0 <= std_logic_vector(unsigned(address(ADDR_WIDTH-1 downto 1)) + 1);
|
a0 <= std_logic_vector(unsigned(address(ADDR_WIDTH-1 downto 1)) + 1);
|
d1 <= data(REG_WIDTH/2-1 downto 0);
|
d1 <= data(REG_WIDTH/2-1 downto 0);
|
d0 <= data(REG_WIDTH-1 downto REG_WIDTH/2);
|
d0 <= data(REG_WIDTH-1 downto REG_WIDTH/2);
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
end if;
|
end if;
|
when MEM_STOREL => if address(0) = '0' then
|
when MEM_STOREL => if address(0) = '0' then
|
wren0 <= '1';
|
wren0 <= '1';
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
d0 <= data(REG_WIDTH/2-1 downto 0);
|
d0 <= data(REG_WIDTH/2-1 downto 0);
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
else
|
else
|
wren1 <= '1';
|
wren1 <= '1';
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
d1 <= data(REG_WIDTH/2-1 downto 0);
|
d1 <= data(REG_WIDTH/2-1 downto 0);
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
end if;
|
end if;
|
when MEM_STOREH => if address(0) = '0' then
|
when MEM_STOREH => if address(0) = '0' then
|
wren0 <= '1';
|
wren0 <= '1';
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
a0 <= address(ADDR_WIDTH-1 downto 1);
|
d0 <= data(REG_WIDTH-1 downto REG_WIDTH/2);
|
d0 <= data(REG_WIDTH-1 downto REG_WIDTH/2);
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
else
|
else
|
wren1 <= '1';
|
wren1 <= '1';
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
a1 <= address(ADDR_WIDTH-1 downto 1);
|
d1 <= data(REG_WIDTH-1 downto REG_WIDTH/2);
|
d1 <= data(REG_WIDTH-1 downto REG_WIDTH/2);
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
end if;
|
end if;
|
when MEM_NOP => next_state <= WAIT_NONE;
|
when MEM_NOP => next_state <= WAIT_NONE;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
elsif unsigned(address) >= unsigned(ROM_MIN_ADDR)
|
elsif unsigned(address) >= unsigned(ROM_MIN_ADDR)
|
and unsigned(address) <= unsigned(ROM_MAX_ADDR) then
|
and unsigned(address) <= unsigned(ROM_MAX_ADDR) then
|
|
|
-- accessing the ROM
|
-- accessing the ROM
|
if op /= MEM_NOP then
|
if op /= MEM_NOP then
|
rom_enable <= '1';
|
rom_enable <= '1';
|
end if;
|
end if;
|
|
|
case state is
|
case state is
|
when WAIT_LOAD_EVEN => result(REG_WIDTH-1 downto REG_WIDTH/2) <= rq1;
|
when WAIT_LOAD_EVEN => result(REG_WIDTH-1 downto REG_WIDTH/2) <= rq1;
|
result(REG_WIDTH/2-1 downto 0) <= rq0;
|
result(REG_WIDTH/2-1 downto 0) <= rq0;
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
|
|
when WAIT_LOAD_ODD => result(REG_WIDTH-1 downto REG_WIDTH/2) <= rq0;
|
when WAIT_LOAD_ODD => result(REG_WIDTH-1 downto REG_WIDTH/2) <= rq0;
|
result(REG_WIDTH/2-1 downto 0) <= rq1;
|
result(REG_WIDTH/2-1 downto 0) <= rq1;
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
|
|
when WAIT_LOADL_EVEN => result(REG_WIDTH-1 downto REG_WIDTH/2) <= old_data(REG_WIDTH-1 downto REG_WIDTH/2);
|
when WAIT_LOADL_EVEN => result(REG_WIDTH-1 downto REG_WIDTH/2) <= old_data(REG_WIDTH-1 downto REG_WIDTH/2);
|
result(REG_WIDTH/2-1 downto 0) <= rq0;
|
result(REG_WIDTH/2-1 downto 0) <= rq0;
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
|
|
when WAIT_LOADL_ODD => result(REG_WIDTH-1 downto REG_WIDTH/2) <= old_data(REG_WIDTH-1 downto REG_WIDTH/2);
|
when WAIT_LOADL_ODD => result(REG_WIDTH-1 downto REG_WIDTH/2) <= old_data(REG_WIDTH-1 downto REG_WIDTH/2);
|
result(REG_WIDTH/2-1 downto 0) <= rq1;
|
result(REG_WIDTH/2-1 downto 0) <= rq1;
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
|
|
when WAIT_LOADH_EVEN => result(REG_WIDTH-1 downto REG_WIDTH/2) <= rq0;
|
when WAIT_LOADH_EVEN => result(REG_WIDTH-1 downto REG_WIDTH/2) <= rq0;
|
result(REG_WIDTH/2-1 downto 0) <= old_data(REG_WIDTH/2-1 downto 0);
|
result(REG_WIDTH/2-1 downto 0) <= old_data(REG_WIDTH/2-1 downto 0);
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
|
|
when WAIT_LOADH_ODD => result(REG_WIDTH-1 downto REG_WIDTH/2) <= rq1;
|
when WAIT_LOADH_ODD => result(REG_WIDTH-1 downto REG_WIDTH/2) <= rq1;
|
result(REG_WIDTH/2-1 downto 0) <= old_data(REG_WIDTH/2-1 downto 0);
|
result(REG_WIDTH/2-1 downto 0) <= old_data(REG_WIDTH/2-1 downto 0);
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
|
|
when WAIT_LOADB_EVEN => result <= std_logic_vector(resize(signed(rq0), REG_WIDTH));
|
when WAIT_LOADB_EVEN => result <= std_logic_vector(resize(signed(rq0), REG_WIDTH));
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
|
|
when WAIT_LOADB_ODD => result <= std_logic_vector(resize(signed(rq1), REG_WIDTH));
|
when WAIT_LOADB_ODD => result <= std_logic_vector(resize(signed(rq1), REG_WIDTH));
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
|
|
when WAIT_NONE =>
|
when WAIT_NONE =>
|
case op is
|
case op is
|
when MEM_LOAD => if address(0) = '0' then
|
when MEM_LOAD => if address(0) = '0' then
|
ra0 <= address(RADDR_WIDTH-1 downto 1);
|
ra0 <= address(RADDR_WIDTH-1 downto 1);
|
ra1 <= address(RADDR_WIDTH-1 downto 1);
|
ra1 <= address(RADDR_WIDTH-1 downto 1);
|
next_state <= WAIT_LOAD_EVEN;
|
next_state <= WAIT_LOAD_EVEN;
|
else
|
else
|
ra1 <= address(RADDR_WIDTH-1 downto 1);
|
ra1 <= address(RADDR_WIDTH-1 downto 1);
|
ra0 <= std_logic_vector(unsigned(address(RADDR_WIDTH-1 downto 1)) + 1);
|
ra0 <= std_logic_vector(unsigned(address(RADDR_WIDTH-1 downto 1)) + 1);
|
next_state <= WAIT_LOAD_ODD;
|
next_state <= WAIT_LOAD_ODD;
|
end if;
|
end if;
|
when MEM_LOADL => if address(0) = '0' then
|
when MEM_LOADL => if address(0) = '0' then
|
ra0 <= address(RADDR_WIDTH-1 downto 1);
|
ra0 <= address(RADDR_WIDTH-1 downto 1);
|
next_state <= WAIT_LOADL_EVEN;
|
next_state <= WAIT_LOADL_EVEN;
|
else
|
else
|
ra1 <= address(RADDR_WIDTH-1 downto 1);
|
ra1 <= address(RADDR_WIDTH-1 downto 1);
|
next_state <= WAIT_LOADL_ODD;
|
next_state <= WAIT_LOADL_ODD;
|
end if;
|
end if;
|
when MEM_LOADH => if address(0) = '0' then
|
when MEM_LOADH => if address(0) = '0' then
|
ra0 <= address(RADDR_WIDTH-1 downto 1);
|
ra0 <= address(RADDR_WIDTH-1 downto 1);
|
next_state <= WAIT_LOADH_EVEN;
|
next_state <= WAIT_LOADH_EVEN;
|
else
|
else
|
ra1 <= address(RADDR_WIDTH-1 downto 1);
|
ra1 <= address(RADDR_WIDTH-1 downto 1);
|
next_state <= WAIT_LOADH_ODD;
|
next_state <= WAIT_LOADH_ODD;
|
end if;
|
end if;
|
when MEM_LOADB => if address(0) = '0' then
|
when MEM_LOADB => if address(0) = '0' then
|
ra0 <= address(RADDR_WIDTH-1 downto 1);
|
ra0 <= address(RADDR_WIDTH-1 downto 1);
|
next_state <= WAIT_LOADB_EVEN;
|
next_state <= WAIT_LOADB_EVEN;
|
else
|
else
|
ra1 <= address(RADDR_WIDTH-1 downto 1);
|
ra1 <= address(RADDR_WIDTH-1 downto 1);
|
next_state <= WAIT_LOADB_ODD;
|
next_state <= WAIT_LOADB_ODD;
|
end if;
|
end if;
|
when MEM_NOP => next_state <= WAIT_NONE;
|
when MEM_NOP => next_state <= WAIT_NONE;
|
when others => exc <= '1'; -- inhibit invalid operations
|
when others => exc <= '1'; -- inhibit invalid operations
|
end case;
|
end case;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
elsif unsigned(address) >= unsigned(SC_MIN_ADDR)
|
elsif unsigned(address) >= unsigned(SC_MIN_ADDR)
|
and unsigned(address) <= unsigned(SC_MAX_ADDR)
|
and unsigned(address) <= unsigned(SC_MAX_ADDR)
|
and address(0) = '0' then
|
and address(0) = '0' then
|
|
|
-- access via SimpCon interface
|
-- access via SimpCon interface
|
case state is
|
case state is
|
|
|
when WAIT_LOAD_EVEN =>
|
when WAIT_LOAD_EVEN =>
|
if sc_output.rdy_cnt /= "00" then
|
if sc_output.rdy_cnt /= "00" then
|
next_state <= WAIT_LOAD_EVEN;
|
next_state <= WAIT_LOAD_EVEN;
|
else
|
else
|
result <= sc_output.rd_data;
|
result <= sc_output.rd_data;
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
end if;
|
end if;
|
|
|
when WAIT_STORE =>
|
when WAIT_STORE =>
|
if sc_output.rdy_cnt /= "00" then
|
if sc_output.rdy_cnt /= "00" then
|
next_state <= WAIT_STORE;
|
next_state <= WAIT_STORE;
|
else
|
else
|
next_state <= WAIT_NONE;
|
next_state <= WAIT_NONE;
|
end if;
|
end if;
|
|
|
when WAIT_NONE =>
|
when WAIT_NONE =>
|
case op is
|
case op is
|
|
|
when MEM_LOAD =>
|
when MEM_LOAD =>
|
sc_input.address <= address(SC_ADDR_WIDTH downto 1);
|
sc_input.address <= address(SC_ADDR_WIDTH downto 1);
|
sc_input.wr <= '0';
|
sc_input.wr <= '0';
|
sc_input.wr_data <= (others => '0');
|
sc_input.wr_data <= (others => '0');
|
sc_input.rd <= '1';
|
sc_input.rd <= '1';
|
next_state <= WAIT_LOAD_EVEN;
|
next_state <= WAIT_LOAD_EVEN;
|
|
|
when MEM_STORE =>
|
when MEM_STORE =>
|
sc_input.address <= address(SC_ADDR_WIDTH downto 1);
|
sc_input.address <= address(SC_ADDR_WIDTH downto 1);
|
sc_input.wr <= '1';
|
sc_input.wr <= '1';
|
sc_input.wr_data <= data;
|
sc_input.wr_data <= data;
|
sc_input.rd <= '0';
|
sc_input.rd <= '0';
|
next_state <= WAIT_STORE;
|
next_state <= WAIT_STORE;
|
|
|
when MEM_NOP => next_state <= WAIT_NONE;
|
when MEM_NOP => next_state <= WAIT_NONE;
|
|
|
when others => exc <= '1'; -- inhibit invalid operations
|
when others => exc <= '1'; -- inhibit invalid operations
|
|
|
end case;
|
end case;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
else
|
else
|
-- invalid address and/or alignment
|
-- invalid address and/or alignment
|
if op /= MEM_NOP then
|
if op /= MEM_NOP then
|
exc <= '1';
|
exc <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
end process readwrite;
|
end process readwrite;
|
|
|
end behaviour;
|
end behaviour;
|
|
|