-- This file is part of the marca processor.
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-- This file is part of the marca processor.
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- This program is free software; you can redistribute it and/or modify it
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-- This program is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU Library General Public License as published
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-- under the terms of the GNU Library General Public License as published
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- any later version.
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-- any later version.
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Library General Public License for more details.
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-- Library General Public License for more details.
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-- You should have received a copy of the GNU Library General Public
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-- You should have received a copy of the GNU Library General Public
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-- License along with this program; if not, write to the Free Software
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-- License along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- MARCA multiplier
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-- MARCA multiplier
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- architecture for a bit-serial multiplier
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-- architecture for a bit-serial multiplier
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Wolfgang Puffitsch
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-- Wolfgang Puffitsch
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-- Computer Architecture Lab, Group 3
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-- Computer Architecture Lab, Group 3
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.marca_pkg.all;
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use work.marca_pkg.all;
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architecture behaviour of multiplier is
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architecture behaviour of multiplier is
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signal reg_busy : std_logic;
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signal reg_busy : std_logic;
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signal reg_operand1 : std_logic_vector(width-1 downto 0);
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signal reg_operand1 : std_logic_vector(width-1 downto 0);
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signal reg_operand2 : std_logic_vector(width-1 downto 0);
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signal reg_operand2 : std_logic_vector(width-1 downto 0);
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signal reg_product : std_logic_vector(width downto 0);
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signal reg_product : std_logic_vector(width downto 0);
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signal reg_hotbit : std_logic_vector(width-1 downto 0);
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signal reg_hotbit : std_logic_vector(width-1 downto 0);
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signal next_busy : std_logic;
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signal next_busy : std_logic;
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signal next_operand1 : std_logic_vector(width-1 downto 0);
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signal next_operand1 : std_logic_vector(width-1 downto 0);
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signal next_operand2 : std_logic_vector(width-1 downto 0);
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signal next_operand2 : std_logic_vector(width-1 downto 0);
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signal next_product : std_logic_vector(width downto 0);
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signal next_product : std_logic_vector(width downto 0);
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signal next_hotbit : std_logic_vector(width-1 downto 0);
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signal next_hotbit : std_logic_vector(width-1 downto 0);
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begin -- behaviour
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begin -- behaviour
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busy <= reg_busy;
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busy <= reg_busy;
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product <= reg_product;
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product <= reg_product;
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syn_proc: process (clock, reset)
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syn_proc: process (clock, reset)
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begin -- process sync
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begin -- process sync
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if reset = RESET_ACTIVE then -- asynchronous reset (active low)
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if reset = RESET_ACTIVE then -- asynchronous reset (active low)
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reg_busy <= '0';
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reg_busy <= '0';
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reg_operand1 <= (others => '0');
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reg_operand1 <= (others => '0');
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reg_operand2 <= (others => '0');
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reg_operand2 <= (others => '0');
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reg_product <= (others => '0');
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reg_product <= (others => '0');
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reg_hotbit <= (others => '0');
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reg_hotbit <= (others => '0');
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reg_hotbit(0) <= '1';
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reg_hotbit(0) <= '1';
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elsif clock'event and clock = '1' then -- rising clock edge
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elsif clock'event and clock = '1' then -- rising clock edge
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if trigger = '1' then
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if trigger = '1' then
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reg_operand1 <= operand1;
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reg_operand1 <= operand1;
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reg_operand2 <= operand2;
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reg_operand2 <= operand2;
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reg_product <= (others => '0');
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reg_product <= (others => '0');
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reg_hotbit(width-1) <= '1';
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reg_hotbit(width-1) <= '1';
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reg_hotbit(width-2 downto 0) <= (others => '0');
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reg_hotbit(width-2 downto 0) <= (others => '0');
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reg_busy <= '1';
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reg_busy <= '1';
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else
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else
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reg_operand1 <= next_operand1;
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reg_operand1 <= next_operand1;
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reg_operand2 <= next_operand2;
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reg_operand2 <= next_operand2;
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reg_product(width-1 downto 0) <= next_product(width-1 downto 0);
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reg_product(width-1 downto 0) <= next_product(width-1 downto 0);
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-- sticky "carry"-bit
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-- sticky "carry"-bit
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reg_product(width) <= reg_product(width) or next_product(width);
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reg_product(width) <= reg_product(width) or next_product(width);
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reg_hotbit <= next_hotbit;
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reg_hotbit <= next_hotbit;
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reg_busy <= next_busy;
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reg_busy <= next_busy;
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end if;
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end if;
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end if;
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end if;
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end process syn_proc;
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end process syn_proc;
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compute: process (reg_operand1, reg_operand2, reg_product, reg_hotbit)
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compute: process (reg_operand1, reg_operand2, reg_product, reg_hotbit)
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begin -- process compute
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begin -- process compute
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next_operand1 <= reg_operand1(width-2 downto 0) & '0';
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next_operand1 <= reg_operand1(width-2 downto 0) & '0';
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next_operand2 <= '0' & reg_operand2(width-1 downto 1);
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next_operand2 <= '0' & reg_operand2(width-1 downto 1);
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next_hotbit <= '0' & reg_hotbit(width-1 downto 1);
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next_hotbit <= '0' & reg_hotbit(width-1 downto 1);
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if reg_hotbit(0) = '1' then
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if reg_hotbit(0) = '1' then
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next_hotbit <= reg_hotbit;
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next_hotbit <= reg_hotbit;
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next_busy <= '0';
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next_busy <= '0';
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else
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else
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next_busy <= '1';
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next_busy <= '1';
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end if;
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end if;
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if reg_operand2(0) = '1' then
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if reg_operand2(0) = '1' then
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next_product <= std_logic_vector(unsigned(reg_product) + unsigned(reg_operand1(width-1 downto 0)));
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next_product <= std_logic_vector(unsigned(reg_product) + unsigned(reg_operand1(width-1 downto 0)));
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else
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else
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next_product <= reg_product;
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next_product <= reg_product;
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end if;
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end if;
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end process compute;
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end process compute;
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end behaviour;
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end behaviour;
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