-- This file is part of the marca processor.
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-- This file is part of the marca processor.
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- This program is free software; you can redistribute it and/or modify it
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-- This program is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU Library General Public License as published
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-- under the terms of the GNU Library General Public License as published
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- any later version.
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-- any later version.
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Library General Public License for more details.
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-- Library General Public License for more details.
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-- You should have received a copy of the GNU Library General Public
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-- You should have received a copy of the GNU Library General Public
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-- License along with this program; if not, write to the Free Software
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-- License along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- MARCA decode stage
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-- MARCA decode stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- architecture for the instruction-decode pipeline stage
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-- architecture for the instruction-decode pipeline stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Wolfgang Puffitsch
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-- Wolfgang Puffitsch
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-- Computer Architecture Lab, Group 3
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-- Computer Architecture Lab, Group 3
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.marca_pkg.all;
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use work.marca_pkg.all;
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architecture behaviour of regfile is
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architecture behaviour of regfile is
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type registers is array (REG_COUNT-1 downto 0) of std_logic_vector(REG_WIDTH-1 downto 0);
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type registers is array (REG_COUNT-1 downto 0) of std_logic_vector(REG_WIDTH-1 downto 0);
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signal regs, next_regs : registers;
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signal regs, next_regs : registers;
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begin -- behaviour
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begin -- behaviour
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syn_proc: process (clock, reset)
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syn_proc: process (clock, reset)
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begin -- process syn_proc
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begin -- process syn_proc
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if reset = RESET_ACTIVE then -- asynchronous reset (active low)
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if reset = RESET_ACTIVE then -- asynchronous reset (active low)
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regs <= (others => (others => '0'));
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regs <= (others => (others => '0'));
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elsif clock'event and clock = '1' then -- rising clock edge
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elsif clock'event and clock = '1' then -- rising clock edge
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if hold = '0' then
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if hold = '0' then
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regs <= next_regs;
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regs <= next_regs;
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end if;
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end if;
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end if;
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end if;
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end process syn_proc;
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end process syn_proc;
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forward: process(rd1_addr, rd2_addr, wr_ena, wr_addr, wr_val, regs)
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forward: process(rd1_addr, rd2_addr, wr_ena, wr_addr, wr_val, regs)
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begin -- process forward
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begin -- process forward
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next_regs <= regs;
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next_regs <= regs;
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if wr_ena = '1' then
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if wr_ena = '1' then
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next_regs(to_integer(unsigned(wr_addr))) <= wr_val;
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next_regs(to_integer(unsigned(wr_addr))) <= wr_val;
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end if;
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end if;
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if rd1_addr /= wr_addr or wr_ena = '0' then
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if rd1_addr /= wr_addr or wr_ena = '0' then
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rd1_val <= regs(to_integer(unsigned(rd1_addr)));
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rd1_val <= regs(to_integer(unsigned(rd1_addr)));
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else
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else
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rd1_val <= wr_val;
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rd1_val <= wr_val;
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end if;
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end if;
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if rd2_addr /= wr_addr or wr_ena = '0' then
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if rd2_addr /= wr_addr or wr_ena = '0' then
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rd2_val <= regs(to_integer(unsigned(rd2_addr)));
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rd2_val <= regs(to_integer(unsigned(rd2_addr)));
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else
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else
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rd2_val <= wr_val;
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rd2_val <= wr_val;
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end if;
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end if;
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end process forward;
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end process forward;
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end behaviour;
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end behaviour;
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