-- This file is part of the marca processor.
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-- This file is part of the marca processor.
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- This program is free software; you can redistribute it and/or modify it
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-- This program is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU Library General Public License as published
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-- under the terms of the GNU Library General Public License as published
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- any later version.
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-- any later version.
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Library General Public License for more details.
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-- Library General Public License for more details.
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-- You should have received a copy of the GNU Library General Public
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-- You should have received a copy of the GNU Library General Public
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-- License along with this program; if not, write to the Free Software
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-- License along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Package SC
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-- Package SC
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- definitions for the SimpCon interface
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-- definitions for the SimpCon interface
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Wolfgang Puffitsch
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-- Wolfgang Puffitsch
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-- Computer Architecture Lab, Group 3
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-- Computer Architecture Lab, Group 3
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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use work.marca_pkg.all;
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use work.marca_pkg.all;
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package sc_pkg is
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package sc_pkg is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- general configuration
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-- general configuration
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant SC_ADDR_WIDTH : integer := 2;
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constant SC_ADDR_WIDTH : integer := 2;
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constant SC_REG_WIDTH : integer := 16;
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constant SC_REG_WIDTH : integer := 16;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- where to access SimCon modules
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-- where to access SimCon modules
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant SC_MIN_ADDR : std_logic_vector := "1111111111111000";
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constant SC_MIN_ADDR : std_logic_vector := "1111111111111000";
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constant SC_MAX_ADDR : std_logic_vector := "1111111111111111";
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constant SC_MAX_ADDR : std_logic_vector := "1111111111111111";
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- records for simpler interfacing
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-- records for simpler interfacing
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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type SC_IN is record
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type SC_IN is record
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address : std_logic_vector(SC_ADDR_WIDTH-1 downto 0);
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address : std_logic_vector(SC_ADDR_WIDTH-1 downto 0);
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wr : std_logic;
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wr : std_logic;
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wr_data : std_logic_vector(SC_REG_WIDTH-1 downto 0);
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wr_data : std_logic_vector(SC_REG_WIDTH-1 downto 0);
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rd : std_logic;
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rd : std_logic;
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end record;
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end record;
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constant SC_IN_NULL : SC_IN := ((others => '0'), '0', (others => '0'), '0');
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constant SC_IN_NULL : SC_IN := ((others => '0'), '0', (others => '0'), '0');
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type SC_OUT is record
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type SC_OUT is record
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rd_data : std_logic_vector(SC_REG_WIDTH-1 downto 0);
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rd_data : std_logic_vector(SC_REG_WIDTH-1 downto 0);
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rdy_cnt : unsigned(1 downto 0);
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rdy_cnt : unsigned(1 downto 0);
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end record;
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end record;
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constant SC_OUT_NULL : SC_OUT := ((others => '0'), "00");
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constant SC_OUT_NULL : SC_OUT := ((others => '0'), "00");
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- output bits
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-- output bits
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant UART_TXD : integer := 0;
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constant UART_TXD : integer := 0;
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constant UART_NRTS : integer := 1;
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constant UART_NRTS : integer := 1;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- input bits
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-- input bits
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant UART_RXD : integer := 0;
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constant UART_RXD : integer := 0;
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constant UART_NCTS : integer := 1;
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constant UART_NCTS : integer := 1;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- interrupt numbers, >= 3
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-- interrupt numbers, >= 3
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant UART_INTR : integer := 3;
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constant UART_INTR : integer := 3;
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- UART configuration
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-- UART configuration
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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constant UART_BASE_ADDR : std_logic_vector(REG_WIDTH-1 downto SC_ADDR_WIDTH+1) := "1111111111111";
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constant UART_BASE_ADDR : std_logic_vector(REG_WIDTH-1 downto SC_ADDR_WIDTH+1) := "1111111111111";
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constant UART_BAUD_RATE : integer := 115200;
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constant UART_BAUD_RATE : integer := 115200;
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end sc_pkg;
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end sc_pkg;
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