-- This file is part of the marca processor.
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-- This file is part of the marca processor.
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- Copyright (C) 2007 Wolfgang Puffitsch
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-- This program is free software; you can redistribute it and/or modify it
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-- This program is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU Library General Public License as published
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-- under the terms of the GNU Library General Public License as published
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- by the Free Software Foundation; either version 2, or (at your option)
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-- any later version.
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-- any later version.
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Library General Public License for more details.
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-- Library General Public License for more details.
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-- You should have received a copy of the GNU Library General Public
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-- You should have received a copy of the GNU Library General Public
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-- License along with this program; if not, write to the Free Software
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-- License along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- MARCA write-back stage
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-- MARCA write-back stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- architecture of the write-back pipeline stage
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-- architecture of the write-back pipeline stage
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Wolfgang Puffitsch
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-- Wolfgang Puffitsch
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-- Computer Architecture Lab, Group 3
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-- Computer Architecture Lab, Group 3
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use work.marca_pkg.all;
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use work.marca_pkg.all;
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architecture behaviour of writeback is
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architecture behaviour of writeback is
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signal pcchg_reg : std_logic;
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signal pcchg_reg : std_logic;
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signal pc_reg : std_logic_vector(REG_WIDTH-1 downto 0);
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signal pc_reg : std_logic_vector(REG_WIDTH-1 downto 0);
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signal dest_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
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signal dest_reg : std_logic_vector(REG_COUNT_LOG-1 downto 0);
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signal result_reg : std_logic_vector(REG_WIDTH-1 downto 0);
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signal result_reg : std_logic_vector(REG_WIDTH-1 downto 0);
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signal target_reg : TARGET_SELECTOR;
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signal target_reg : TARGET_SELECTOR;
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begin -- behaviour
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begin -- behaviour
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syn_proc: process (clock, reset)
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syn_proc: process (clock, reset)
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begin -- process syn_proc
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begin -- process syn_proc
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if reset = RESET_ACTIVE then -- asynchronous reset (active low)
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if reset = RESET_ACTIVE then -- asynchronous reset (active low)
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pcchg_reg <= '0';
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pcchg_reg <= '0';
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pc_reg <= (others => '0');
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pc_reg <= (others => '0');
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dest_reg <= (others => '0');
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dest_reg <= (others => '0');
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result_reg <= (others => '0');
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result_reg <= (others => '0');
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target_reg <= TARGET_NONE;
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target_reg <= TARGET_NONE;
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elsif clock'event and clock = '1' then -- rising clock edge
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elsif clock'event and clock = '1' then -- rising clock edge
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if hold = '0' then
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if hold = '0' then
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pcchg_reg <= pcchg;
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pcchg_reg <= pcchg;
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pc_reg <= pc_in;
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pc_reg <= pc_in;
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dest_reg <= dest_in;
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dest_reg <= dest_in;
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target_reg <= target;
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target_reg <= target;
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result_reg <= result;
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result_reg <= result;
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end if;
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end if;
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end if;
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end if;
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end process syn_proc;
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end process syn_proc;
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dispatch: process (target_reg, pcchg_reg, pc_reg, result_reg, dest_reg)
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dispatch: process (target_reg, pcchg_reg, pc_reg, result_reg, dest_reg)
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begin -- process dispatch
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begin -- process dispatch
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pcena <= '0';
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pcena <= '0';
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pc_out <= pc_reg;
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pc_out <= pc_reg;
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ena <= '0';
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ena <= '0';
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dest_out <= dest_reg;
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dest_out <= dest_reg;
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val <= result_reg;
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val <= result_reg;
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case target_reg is
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case target_reg is
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when TARGET_REGISTER =>
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when TARGET_REGISTER =>
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ena <= '1';
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ena <= '1';
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when TARGET_PC =>
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when TARGET_PC =>
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if pcchg_reg = '1' then
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if pcchg_reg = '1' then
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pcena <= '1';
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pcena <= '1';
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pc_out <= result_reg;
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pc_out <= result_reg;
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end if;
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end if;
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when TARGET_BOTH =>
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when TARGET_BOTH =>
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pcena <= '1';
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pcena <= '1';
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ena <= '1';
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ena <= '1';
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when others => null;
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when others => null;
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end case;
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end case;
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end process dispatch;
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end process dispatch;
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end behaviour;
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end behaviour;
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