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----------------------------------------------------------------------------------------------
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--
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--
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-- Input file : config_Pkg.vhd
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-- Input file : config_Pkg.vhd
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-- Design name : config_Pkg
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-- Design name : config_Pkg
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-- Author : Tamar Kranenburg
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-- Author : Tamar Kranenburg
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-- Company : Delft University of Technology
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-- Company : Delft University of Technology
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-- : Faculty EEMCS, Department ME&CE
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-- : Faculty EEMCS, Department ME&CE
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-- : Systems and Circuits group
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-- : Systems and Circuits group
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--
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--
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-- Description : Testbench instantiates mblite_soc and stdio
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-- Description : Testbench instantiates mblite_soc and stdio
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--
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--
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----------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.ALL;
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USE ieee.std_logic_unsigned.ALL;
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LIBRARY std;
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LIBRARY std;
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USE std.textio.ALL;
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USE std.textio.ALL;
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LIBRARY mblite;
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LIBRARY mblite;
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USE mblite.config_Pkg.ALL;
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USE mblite.config_Pkg.ALL;
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USE mblite.core_Pkg.ALL;
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USE mblite.core_Pkg.ALL;
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USE mblite.std_Pkg.ALL;
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USE mblite.std_Pkg.ALL;
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ENTITY testbench IS
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ENTITY testbench IS
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END testbench;
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END testbench;
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ARCHITECTURE arch OF testbench IS
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ARCHITECTURE arch OF testbench IS
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COMPONENT mblite_soc IS PORT
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COMPONENT mblite_soc IS PORT
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(
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(
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sys_clk_i : in STD_LOGIC := 'X';
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sys_clk_i : in STD_LOGIC := 'X';
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dbg_dmem_o_we_o : out STD_LOGIC;
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dbg_dmem_o_we_o : out STD_LOGIC;
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dbg_dmem_o_ena_o : out STD_LOGIC;
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dbg_dmem_o_ena_o : out STD_LOGIC;
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sys_rst_i : in STD_LOGIC := 'X';
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sys_rst_i : in STD_LOGIC := 'X';
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sys_ena_i : in STD_LOGIC := 'X';
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sys_ena_i : in STD_LOGIC := 'X';
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sys_int_i : in STD_LOGIC := 'X';
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sys_int_i : in STD_LOGIC := 'X';
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dbg_dmem_o_adr_o : out STD_LOGIC_VECTOR(31 downto 0);
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dbg_dmem_o_adr_o : out STD_LOGIC_VECTOR(31 downto 0);
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dbg_dmem_o_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
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dbg_dmem_o_dat_o : out STD_LOGIC_VECTOR(31 downto 0);
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dbg_dmem_o_sel_o : out STD_LOGIC_VECTOR( 3 downto 0)
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dbg_dmem_o_sel_o : out STD_LOGIC_VECTOR( 3 downto 0)
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);
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);
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END COMPONENT;
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END COMPONENT;
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SIGNAL sys_clk_i : std_ulogic := '0';
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SIGNAL sys_clk_i : std_logic := '0';
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SIGNAL sys_int_i : std_ulogic := '0';
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SIGNAL sys_int_i : std_logic := '0';
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SIGNAL sys_rst_i : std_ulogic := '0';
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SIGNAL sys_rst_i : std_logic := '0';
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SIGNAL sys_ena_i : std_ulogic := '1';
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SIGNAL sys_ena_i : std_logic := '1';
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SIGNAL dmem_o : dmem_out_type;
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SIGNAL dmem_o : dmem_out_type;
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CONSTANT std_out_adr : std_ulogic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
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CONSTANT std_out_adr : std_logic_vector(CFG_DMEM_SIZE - 1 DOWNTO 0) := X"FFFFFFC0";
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BEGIN
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BEGIN
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sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
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sys_clk_i <= NOT sys_clk_i AFTER 10000 ps;
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sys_rst_i <= '1' AFTER 0 ps, '0' AFTER 150000 ps;
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sys_rst_i <= '1' AFTER 0 ps, '0' AFTER 150000 ps;
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sys_int_i <= '1' AFTER 500000000 ps, '0' after 500040000 ps;
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sys_int_i <= '1' AFTER 500000000 ps, '0' after 500040000 ps;
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soc : mblite_soc PORT MAP
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soc : mblite_soc PORT MAP
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(
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(
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sys_clk_i => sys_clk_i,
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sys_clk_i => sys_clk_i,
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dbg_dmem_o_we_o => dmem_o.we_o,
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dbg_dmem_o_we_o => dmem_o.we_o,
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dbg_dmem_o_ena_o => dmem_o.ena_o,
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dbg_dmem_o_ena_o => dmem_o.ena_o,
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sys_rst_i => sys_rst_i,
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sys_rst_i => sys_rst_i,
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sys_ena_i => sys_ena_i,
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sys_ena_i => sys_ena_i,
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sys_int_i => sys_int_i,
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sys_int_i => sys_int_i,
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dbg_dmem_o_adr_o => dmem_o.adr_o,
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dbg_dmem_o_adr_o => dmem_o.adr_o,
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dbg_dmem_o_dat_o => dmem_o.dat_o,
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dbg_dmem_o_dat_o => dmem_o.dat_o,
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dbg_dmem_o_sel_o => dmem_o.sel_o
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dbg_dmem_o_sel_o => dmem_o.sel_o
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);
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);
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timeout: PROCESS(sys_clk_i)
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timeout: PROCESS(sys_clk_i)
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BEGIN
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BEGIN
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IF NOW = 10 ms THEN
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IF NOW = 10 ms THEN
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REPORT "TIMEOUT" SEVERITY FAILURE;
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REPORT "TIMEOUT" SEVERITY FAILURE;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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-- Character device
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-- Character device
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stdio: PROCESS(sys_clk_i)
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stdio: PROCESS(sys_clk_i)
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VARIABLE s : line;
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VARIABLE s : line;
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VARIABLE byte : std_ulogic_vector(7 DOWNTO 0);
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VARIABLE byte : std_logic_vector(7 DOWNTO 0);
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VARIABLE char : character;
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VARIABLE char : character;
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BEGIN
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BEGIN
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IF rising_edge(sys_clk_i) THEN
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IF rising_edge(sys_clk_i) THEN
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IF (NOT sys_rst_i AND dmem_o.ena_o AND compare(dmem_o.adr_o, std_out_adr)) = '1' THEN
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IF (NOT sys_rst_i AND dmem_o.ena_o AND compare(dmem_o.adr_o, std_out_adr)) = '1' THEN
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IF dmem_o.we_o = '1' THEN
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IF dmem_o.we_o = '1' THEN
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-- WRITE STDOUT
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-- WRITE STDOUT
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CASE dmem_o.sel_o IS
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CASE dmem_o.sel_o IS
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WHEN "0001" => byte := dmem_o.dat_o( 7 DOWNTO 0);
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WHEN "0001" => byte := dmem_o.dat_o( 7 DOWNTO 0);
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WHEN "0010" => byte := dmem_o.dat_o(15 DOWNTO 8);
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WHEN "0010" => byte := dmem_o.dat_o(15 DOWNTO 8);
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WHEN "0100" => byte := dmem_o.dat_o(23 DOWNTO 16);
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WHEN "0100" => byte := dmem_o.dat_o(23 DOWNTO 16);
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WHEN "1000" => byte := dmem_o.dat_o(31 DOWNTO 24);
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WHEN "1000" => byte := dmem_o.dat_o(31 DOWNTO 24);
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WHEN OTHERS => NULL;
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WHEN OTHERS => NULL;
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END CASE;
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END CASE;
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char := character'val(my_conv_integer(byte));
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char := character'val(my_conv_integer(byte));
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IF byte = X"0D" THEN
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IF byte = X"0D" THEN
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-- Ignore character 13
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-- Ignore character 13
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ELSIF byte = X"0A" THEN
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ELSIF byte = X"0A" THEN
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-- Writeline on character 10 (newline)
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-- Writeline on character 10 (newline)
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writeline(output, s);
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writeline(output, s);
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ELSE
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ELSE
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-- Write to buffer
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-- Write to buffer
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write(s, char);
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write(s, char);
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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END arch;
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END arch;
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