`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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`default_nettype none
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//
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//
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// 4004 Counter sub-module
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// MCS-4 common counter sub-module
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//
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// This module emulates the counter logic found in Intel MCS-4
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// integrated circuits such as the i4004 CPU.
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//
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//
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// This file is part of the MCS-4 project hosted at OpenCores:
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// This file is part of the MCS-4 project hosted at OpenCores:
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// http://www.opencores.org/cores/mcs-4/
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// http://www.opencores.org/cores/mcs-4/
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//
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//
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// Copyright © 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
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// Copyright © 2012, 2021 by Reece Pollack <rrpollack@opencores.org>
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//
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//
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// These materials are provided under the Creative Commons
|
// These materials are provided under the Creative Commons
|
// "Attribution-NonCommercial-ShareAlike" Public License. They
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// "Attribution-NonCommercial-ShareAlike" (CC BY-NC-SA) Public License.
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// are NOT "public domain" and are protected by copyright.
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// They are NOT "public domain", and are protected by copyright.
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//
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//
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// This work based on materials provided by Intel Corporation and
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// This work based on materials provided by Intel Corporation and
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// others under the same license. See the file doc/License for
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// others under the same license. See the file doc/License for
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// details of this license.
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// details of this license.
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//
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//
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////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////
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module counter(
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module counter (
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input wire sysclk,
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input wire sysclk,
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input wire step_a,
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input wire step_b,
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input wire step_a_in,
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output reg q = 1'b0
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input wire step_b_in,
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output wire step_a_out,
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output wire step_b_out,
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output wire q,
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output wire qn
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);
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);
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reg q_n = 1'b1;
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reg master = 1'b0;
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reg slave = 1'b0;
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always @(posedge sysclk) begin
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if (step_a_in)
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master <= ~slave;
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end
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always @(posedge sysclk) begin
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always @(posedge sysclk) begin
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if (step_a) q <= ~q_n;
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if (step_b_in)
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if (step_b) q_n <= q;
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slave <= master;
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end
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end
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assign step_a_out = slave;
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assign step_b_out = ~slave;
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assign q = step_a_out;
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assign qn = step_b_out;
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endmodule
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endmodule
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