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[/] [mcs-4/] [trunk/] [rtl/] [verilog/] [common/] [counter.v] - Diff between revs 5 and 6

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Rev 5 Rev 6
`timescale 1ns / 1ps
`timescale 1ns / 1ps
`default_nettype none
`default_nettype none
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// 
// 
// 4004 Counter sub-module
// MCS-4 common counter sub-module
 
//
 
// This module emulates the counter logic found in Intel MCS-4
 
// integrated circuits such as the i4004 CPU.
// 
// 
// This file is part of the MCS-4 project hosted at OpenCores:
// This file is part of the MCS-4 project hosted at OpenCores:
//      http://www.opencores.org/cores/mcs-4/
//      http://www.opencores.org/cores/mcs-4/
// 
// 
// Copyright © 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
// Copyright © 2012, 2021 by Reece Pollack <rrpollack@opencores.org>
// 
// 
// These materials are provided under the Creative Commons
// These materials are provided under the Creative Commons
// "Attribution-NonCommercial-ShareAlike" Public License. They
// "Attribution-NonCommercial-ShareAlike" (CC BY-NC-SA) Public License.
// are NOT "public domain" and are protected by copyright.
// They are NOT "public domain", and are protected by copyright.
// 
// 
// This work based on materials provided by Intel Corporation and
// This work based on materials provided by Intel Corporation and
// others under the same license. See the file doc/License for
// others under the same license. See the file doc/License for
// details of this license.
// details of this license.
//
//
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
 
 
module counter(
module counter (
        input  wire     sysclk,
        input  wire     sysclk,
        input  wire     step_a,
 
        input  wire     step_b,
    input  wire step_a_in,
        output reg      q = 1'b0
    input  wire step_b_in,
 
 
 
    output wire step_a_out,
 
    output wire step_b_out,
 
    output wire q,
 
    output wire qn
        );
        );
 
 
        reg q_n = 1'b1;
    reg  master = 1'b0;
 
    reg  slave  = 1'b0;
 
    always @(posedge sysclk) begin
 
        if (step_a_in)
 
            master <= ~slave;
 
    end
 
 
        always @(posedge sysclk) begin
        always @(posedge sysclk) begin
                if (step_a)     q <= ~q_n;
        if (step_b_in)
                if (step_b) q_n <= q;
            slave  <= master;
        end
        end
 
 
 
    assign step_a_out =  slave;
 
    assign step_b_out = ~slave;
 
 
 
    assign q  = step_a_out;
 
    assign qn = step_b_out;
 
 
endmodule
endmodule
 
 

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