-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
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--
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--
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-- Copyright Jamil Khatib 1999
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-- Copyright Jamil Khatib 1999
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--
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--
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--
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--
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it under the terms of the Openip General Public
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-- modify it and/or implement it under the terms of the Openip General Public
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-- License as it is going to be published by the OpenIP Organization and any
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-- License as it is going to be published by the OpenIP Organization and any
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-- coming versions of this license.
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-- coming versions of this license.
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-- You can check the draft license at
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-- You can check the draft license at
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-- http://www.openip.org/oc/license.html
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-- http://www.openip.org/oc/license.html
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--
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--
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--
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--
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-- Creator : Jamil Khatib
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-- Creator : Jamil Khatib
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-- Date 10/10/99
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-- Date 10/10/99
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--
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--
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-- version 0.19991226
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-- version 0.19991226
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--
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--
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-- This file was tested on the ModelSim 5.2EE
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-- This file was tested on the ModelSim 5.2EE
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-- The test vecors for model sim is included in vectors.do file
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-- The test vecors for model sim is included in vectors.do file
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-- This VHDL design file is proved through simulation but not verified on Silicon
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-- This VHDL design file is proved through simulation but not verified on Silicon
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--
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--
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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|
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USE ieee.std_logic_unsigned.ALL;
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USE ieee.std_logic_unsigned.ALL;
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|
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-- Dual port Memory core
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-- Dual port Memory core
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ENTITY dpmem IS
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ENTITY dpmem IS
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generic ( ADD_WIDTH: integer := 8 ;
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generic ( ADD_WIDTH: integer := 8 ;
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WIDTH : integer := 8);
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WIDTH : integer := 8);
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PORT (
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PORT (
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clk : IN std_logic; -- write clock
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clk : IN std_logic; -- write clock
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reset : IN std_logic; -- System Reset
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reset : IN std_logic; -- System Reset
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W_add : IN std_logic_vector(add_width -1 downto 0); -- Write Address
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W_add : IN std_logic_vector(add_width -1 downto 0); -- Write Address
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R_add : IN std_logic_vector(add_width -1 downto 0); -- Read Address
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R_add : IN std_logic_vector(add_width -1 downto 0); -- Read Address
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Data_In : IN std_logic_vector(WIDTH - 1 DOWNTO 0); -- input data
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Data_In : IN std_logic_vector(WIDTH - 1 DOWNTO 0); -- input data
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Data_Out : OUT std_logic_vector(WIDTH -1 DOWNTO 0); -- output Data
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Data_Out : OUT std_logic_vector(WIDTH -1 DOWNTO 0); -- output Data
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WR : IN std_logic; -- Write Enable
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WR : IN std_logic; -- Write Enable
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RE : IN std_logic); -- Read Enable
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RE : IN std_logic); -- Read Enable
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END dpmem;
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END dpmem;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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ARCHITECTURE dpmem_v3 OF dpmem IS
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ARCHITECTURE dpmem_v3 OF dpmem IS
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TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(WIDTH -1 DOWNTO 0);
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TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(WIDTH -1 DOWNTO 0);
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-- Memory Type
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-- Memory Type
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SIGNAL data : data_array(0 to (2** add_width) ); -- Local data
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SIGNAL data : data_array(0 to (2** add_width) ); -- Local data
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procedure init_mem(signal memory_cell : inout data_array ) is
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procedure init_mem(signal memory_cell : inout data_array ) is
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begin
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begin
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for i in 0 to (2** add_width) loop
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for i in 0 to (2** add_width) loop
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memory_cell(i) <= (others => '0');
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memory_cell(i) <= (others => '0');
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end loop;
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end loop;
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end init_mem;
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end init_mem;
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BEGIN -- dpmem_v3
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BEGIN -- dpmem_v3
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PROCESS (clk, reset)
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PROCESS (clk, reset)
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BEGIN -- PROCESS
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BEGIN -- PROCESS
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-- activities triggered by asynchronous reset (active low)
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-- activities triggered by asynchronous reset (active low)
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IF reset = '0' THEN
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IF reset = '0' THEN
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data_out <= (OTHERS => '1');
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data_out <= (OTHERS => '1');
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init_mem ( data);
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init_mem ( data);
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|
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-- activities triggered by rising edge of clock
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-- activities triggered by rising edge of clock
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ELSIF clk'event AND clk = '1' THEN
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ELSIF clk'event AND clk = '1' THEN
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IF RE = '1' THEN
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IF RE = '1' THEN
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data_out <= data(conv_integer(R_add));
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data_out <= data(conv_integer(R_add));
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else
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else
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data_out <= (OTHERS => '1'); -- Defualt value
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data_out <= (OTHERS => '1'); -- Defualt value
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END IF;
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END IF;
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IF WR = '1' THEN
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IF WR = '1' THEN
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data(conv_integeR(W_add)) <= Data_In;
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data(conv_integeR(W_add)) <= Data_In;
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END IF;
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END IF;
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END IF;
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END IF;
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END PROCESS;
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END PROCESS;
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END dpmem_v3;
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END dpmem_v3;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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USE ieee.std_logic_signed.ALL;
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USE ieee.std_logic_signed.ALL;
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USE ieee.std_logic_arith.ALL;
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USE ieee.std_logic_arith.ALL;
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|
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entity FIFO is
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entity FIFO is
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generic (WIDTH : integer := 8; -- FIFO word width
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generic (WIDTH : integer := 8; -- FIFO word width
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ADD_WIDTH : integer := 8); -- Address Width
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ADD_WIDTH : integer := 8); -- Address Width
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|
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port (Data_in : in std_logic_vector(WIDTH - 1 downto 0); -- Input data
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port (Data_in : in std_logic_vector(WIDTH - 1 downto 0); -- Input data
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Data_out : out std_logic_vector(WIDTH - 1 downto 0); -- Out put data
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Data_out : out std_logic_vector(WIDTH - 1 downto 0); -- Out put data
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clk : in std_logic; -- System Clock
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clk : in std_logic; -- System Clock
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Reset : in std_logic; -- System global Reset
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Reset : in std_logic; -- System global Reset
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RE : in std_logic; -- Read Enable
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RE : in std_logic; -- Read Enable
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WE : in std_logic; -- Write Enable
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WE : in std_logic; -- Write Enable
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Full : buffer std_logic; -- Full Flag
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Full : buffer std_logic; -- Full Flag
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Half_full : out std_logic; -- Half Full Flag
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Half_full : out std_logic; -- Half Full Flag
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Empty : buffer std_logic); -- Empty Flag
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Empty : buffer std_logic); -- Empty Flag
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end FIFO;
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end FIFO;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Input data _is_ latched
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-- Input data _is_ latched
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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--USE ieee.std_logic_signed.ALL;
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--USE ieee.std_logic_signed.ALL;
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--USE ieee.std_logic_arith.ALL;
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--USE ieee.std_logic_arith.ALL;
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|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- purpose: FIFO Architecture
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-- purpose: FIFO Architecture
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architecture FIFO_v1 of FIFO is
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architecture FIFO_v1 of FIFO is
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|
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-- constant values
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-- constant values
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constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
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constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
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constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
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constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
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constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
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constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
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signal Data_in_del : std_logic_vector(WIDTH - 1 downto 0); -- delayed Data in
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signal Data_in_del : std_logic_vector(WIDTH - 1 downto 0); -- delayed Data in
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|
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signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
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signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
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signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
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signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
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signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address
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signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address
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|
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signal REN_INT : std_logic; -- Internal Read Enable
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signal REN_INT : std_logic; -- Internal Read Enable
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signal WEN_INT : std_logic; -- Internal Write Enable
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signal WEN_INT : std_logic; -- Internal Write Enable
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|
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component dpmem
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component dpmem
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generic (ADD_WIDTH : integer := 8;
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generic (ADD_WIDTH : integer := 8;
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WIDTH : integer := 8 );
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WIDTH : integer := 8 );
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|
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port (clk : in std_logic;
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port (clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
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w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
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r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
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r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
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data_in : in std_logic_vector(WIDTH - 1 downto 0);
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data_in : in std_logic_vector(WIDTH - 1 downto 0);
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data_out : out std_logic_vector(WIDTH - 1 downto 0 );
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data_out : out std_logic_vector(WIDTH - 1 downto 0 );
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WR : in std_logic;
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WR : in std_logic;
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RE : in std_logic);
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RE : in std_logic);
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end component;
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end component;
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begin -- FIFO_v1
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begin -- FIFO_v1
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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|
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memcore: dpmem
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memcore: dpmem
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generic map (WIDTH => 8,
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generic map (WIDTH => 8,
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ADD_WIDTH =>8)
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ADD_WIDTH =>8)
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port map (clk => clk,
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port map (clk => clk,
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reset => reset,
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reset => reset,
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w_add => w_add,
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w_add => w_add,
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r_add => r_add,
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r_add => r_add,
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Data_in => data_in_del,
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Data_in => data_in_del,
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data_out => data_out,
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data_out => data_out,
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wr => wen_int,
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wr => wen_int,
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re => ren_int);
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re => ren_int);
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|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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|
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Sync_data: process(clk,reset)
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Sync_data: process(clk,reset)
|
begin -- process Sync_data
|
begin -- process Sync_data
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if reset ='0' then
|
if reset ='0' then
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data_in_del <= (others =>'0');
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data_in_del <= (others =>'0');
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|
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
data_in_del <= data_in;
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data_in_del <= data_in;
|
else
|
else
|
data_in_del <= data_in_del;
|
data_in_del <= data_in_del;
|
end if;
|
end if;
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|
|
|
|
end process Sync_data;
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end process Sync_data;
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|
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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|
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wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
|
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
|
|
|
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
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ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
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|
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--w_r_gen: process(we,re,FULL,EMPTY)
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--w_r_gen: process(we,re,FULL,EMPTY)
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|
|
--begin
|
--begin
|
|
|
-- if WE = '1' and (FULL = '0') then
|
-- if WE = '1' and (FULL = '0') then
|
-- wen_int <= '1';
|
-- wen_int <= '1';
|
-- else
|
-- else
|
-- wen_int <= '0';
|
-- wen_int <= '0';
|
|
|
-- end if;
|
-- end if;
|
|
|
-- if RE = '1' and ( EMPTY = '0') then
|
-- if RE = '1' and ( EMPTY = '0') then
|
-- ren_int <= '1';
|
-- ren_int <= '1';
|
-- else
|
-- else
|
-- ren_int <= '0';
|
-- ren_int <= '0';
|
-- end if;
|
-- end if;
|
|
|
--end process w_r_gen;
|
--end process w_r_gen;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
|
Add_gen: process(clk,reset)
|
Add_gen: process(clk,reset)
|
variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
|
|
begin -- process ADD_gen
|
begin -- process ADD_gen
|
|
|
-- activities triggered by asynchronous reset (active low)
|
-- activities triggered by asynchronous reset (active low)
|
if reset = '0' then
|
if reset = '0' then
|
q1 := (others =>'0');
|
q1 := (others =>'0');
|
q2 := (others =>'0');
|
q2 := (others =>'0');
|
q3 := (others =>'0');
|
q3 := (others =>'0');
|
-- wen_int <= '0';
|
-- wen_int <= '0';
|
-- ren_int <= '0';
|
-- ren_int <= '0';
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
|
|
if WE = '1' and ( FULL = '0') then
|
if WE = '1' and ( FULL = '0') then
|
q1 := q1 + 1;
|
q1 := q1 + 1;
|
q3 := q3 +1;
|
q3 := q3 +1;
|
-- wen_int <= '1';
|
-- wen_int <= '1';
|
else
|
else
|
q1 := q1;
|
q1 := q1;
|
q3 := q3;
|
q3 := q3;
|
--wen_int <= '0';
|
--wen_int <= '0';
|
|
|
end if;
|
end if;
|
|
|
if RE = '1' and ( EMPTY = '0') then
|
if RE = '1' and ( EMPTY = '0') then
|
q2 := q2 + 1;
|
q2 := q2 + 1;
|
q3 := q3 -1;
|
q3 := q3 -1;
|
--ren_int <= '1';
|
--ren_int <= '1';
|
else
|
else
|
q2 := q2;
|
q2 := q2;
|
q3 := q3;
|
q3 := q3;
|
--ren_int <= '0';
|
--ren_int <= '0';
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
R_ADD <= q2;
|
R_ADD <= q2;
|
W_ADD <= q1;
|
W_ADD <= q1;
|
D_ADD <= q3;
|
D_ADD <= q3;
|
|
|
end process ADD_gen;
|
end process ADD_gen;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
|
FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
|
EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0';
|
EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0';
|
HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0';
|
HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0';
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
|
|
|
end FIFO_v1;
|
end FIFO_v1;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Ren_int & Wen_int are synchronized with the clock
|
-- Ren_int & Wen_int are synchronized with the clock
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
--USE ieee.std_logic_signed.ALL;
|
--USE ieee.std_logic_signed.ALL;
|
--USE ieee.std_logic_arith.ALL;
|
--USE ieee.std_logic_arith.ALL;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- purpose: FIFO Architecture
|
-- purpose: FIFO Architecture
|
architecture FIFO_v2 of FIFO is
|
architecture FIFO_v2 of FIFO is
|
|
|
-- constant values
|
-- constant values
|
constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
|
constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
|
constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
|
constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
|
|
|
|
signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
|
signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
|
signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
|
signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
|
signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address
|
signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address
|
|
|
signal REN_INT : std_logic; -- Internal Read Enable
|
signal REN_INT : std_logic; -- Internal Read Enable
|
signal WEN_INT : std_logic; -- Internal Write Enable
|
signal WEN_INT : std_logic; -- Internal Write Enable
|
|
|
component dpmem
|
component dpmem
|
generic (ADD_WIDTH : integer := 8;
|
generic (ADD_WIDTH : integer := 8;
|
WIDTH : integer := 8 );
|
WIDTH : integer := 8 );
|
|
|
port (clk : in std_logic;
|
port (clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_out : out std_logic_vector(WIDTH - 1 downto 0 );
|
data_out : out std_logic_vector(WIDTH - 1 downto 0 );
|
WR : in std_logic;
|
WR : in std_logic;
|
RE : in std_logic);
|
RE : in std_logic);
|
end component;
|
end component;
|
|
|
|
|
|
|
begin -- FIFO_v2
|
begin -- FIFO_v2
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
memcore: dpmem
|
memcore: dpmem
|
generic map (WIDTH => 8,
|
generic map (WIDTH => 8,
|
ADD_WIDTH =>8)
|
ADD_WIDTH =>8)
|
|
|
port map (clk => clk,
|
port map (clk => clk,
|
reset => reset,
|
reset => reset,
|
w_add => w_add,
|
w_add => w_add,
|
r_add => r_add,
|
r_add => r_add,
|
Data_in => data_in,
|
Data_in => data_in,
|
data_out => data_out,
|
data_out => data_out,
|
wr => wen_int,
|
wr => wen_int,
|
re => ren_int);
|
re => ren_int);
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
cont_gen: process(clk,reset)
|
cont_gen: process(clk,reset)
|
begin -- process cont_gen
|
begin -- process cont_gen
|
|
|
-- activities triggered by asynchronous reset (active low)
|
-- activities triggered by asynchronous reset (active low)
|
if reset = '0' then
|
if reset = '0' then
|
wen_int <= '0';
|
wen_int <= '0';
|
ren_int <= '0';
|
ren_int <= '0';
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
|
|
if WE = '1' and (not FULL = '1') then
|
if WE = '1' and (not FULL = '1') then
|
wen_int <= '1';
|
wen_int <= '1';
|
else
|
else
|
wen_int <= '0';
|
wen_int <= '0';
|
|
|
end if;
|
end if;
|
|
|
if RE = '1' and (not EMPTY = '1') then
|
if RE = '1' and (not EMPTY = '1') then
|
ren_int <= '1';
|
ren_int <= '1';
|
else
|
else
|
ren_int <= '0';
|
ren_int <= '0';
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process cont_gen;
|
end process cont_gen;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
Add_gen: process(clk,reset)
|
Add_gen: process(clk,reset)
|
variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
|
|
begin -- process ADD_gen
|
begin -- process ADD_gen
|
|
|
-- activities triggered by asynchronous reset (active low)
|
-- activities triggered by asynchronous reset (active low)
|
if reset = '0' then
|
if reset = '0' then
|
q1 := (others =>'0');
|
q1 := (others =>'0');
|
q2 := (others =>'0');
|
q2 := (others =>'0');
|
q3 := (others =>'0');
|
q3 := (others =>'0');
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
|
|
if WE = '1' and ( FULL = '0') then
|
if WE = '1' and ( FULL = '0') then
|
q1 := q1 + 1;
|
q1 := q1 + 1;
|
q3 := q3 +1;
|
q3 := q3 +1;
|
else
|
else
|
q1 := q1;
|
q1 := q1;
|
q3 := q3;
|
q3 := q3;
|
|
|
end if;
|
end if;
|
|
|
if RE = '1' and ( EMPTY = '0') then
|
if RE = '1' and ( EMPTY = '0') then
|
q2 := q2 + 1;
|
q2 := q2 + 1;
|
q3 := q3 -1;
|
q3 := q3 -1;
|
else
|
else
|
q2 := q2;
|
q2 := q2;
|
q3 := q3;
|
q3 := q3;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
R_ADD <= q2;
|
R_ADD <= q2;
|
W_ADD <= q1;
|
W_ADD <= q1;
|
D_ADD <= q3;
|
D_ADD <= q3;
|
|
|
end process ADD_gen;
|
end process ADD_gen;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
|
FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
|
EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0';
|
EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0';
|
HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0';
|
HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0';
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
end FIFO_v2;
|
end FIFO_v2;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
-- Input data is _NOT_ latched
|
-- Input data is _NOT_ latched
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
--USE ieee.std_logic_signed.ALL;
|
--USE ieee.std_logic_signed.ALL;
|
--USE ieee.std_logic_arith.ALL;
|
--USE ieee.std_logic_arith.ALL;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- purpose: FIFO Architecture
|
-- purpose: FIFO Architecture
|
architecture FIFO_v3 of FIFO is
|
architecture FIFO_v3 of FIFO is
|
|
|
-- constant values
|
-- constant values
|
constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
|
constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
|
constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
|
constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
|
|
|
|
|
|
signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
|
signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
|
signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
|
signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
|
signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address
|
signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address
|
|
|
signal REN_INT : std_logic; -- Internal Read Enable
|
signal REN_INT : std_logic; -- Internal Read Enable
|
signal WEN_INT : std_logic; -- Internal Write Enable
|
signal WEN_INT : std_logic; -- Internal Write Enable
|
|
|
component dpmem
|
component dpmem
|
generic (ADD_WIDTH : integer := 8;
|
generic (ADD_WIDTH : integer := 8;
|
WIDTH : integer := 8 );
|
WIDTH : integer := 8 );
|
|
|
port (clk : in std_logic;
|
port (clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_out : out std_logic_vector(WIDTH - 1 downto 0 );
|
data_out : out std_logic_vector(WIDTH - 1 downto 0 );
|
WR : in std_logic;
|
WR : in std_logic;
|
RE : in std_logic);
|
RE : in std_logic);
|
end component;
|
end component;
|
|
|
|
|
|
|
begin -- FIFO_v3
|
begin -- FIFO_v3
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
memcore: dpmem
|
memcore: dpmem
|
generic map (WIDTH => 8,
|
generic map (WIDTH => 8,
|
ADD_WIDTH =>8)
|
ADD_WIDTH =>8)
|
port map (clk => clk,
|
port map (clk => clk,
|
reset => reset,
|
reset => reset,
|
w_add => w_add,
|
w_add => w_add,
|
r_add => r_add,
|
r_add => r_add,
|
Data_in => data_in,
|
Data_in => data_in,
|
data_out => data_out,
|
data_out => data_out,
|
wr => wen_int,
|
wr => wen_int,
|
re => ren_int);
|
re => ren_int);
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
|
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
|
|
|
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
|
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
Add_gen: process(clk,reset)
|
Add_gen: process(clk,reset)
|
variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q1 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q2 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
variable q3 : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Counter state
|
|
|
begin -- process ADD_gen
|
begin -- process ADD_gen
|
|
|
-- activities triggered by asynchronous reset (active low)
|
-- activities triggered by asynchronous reset (active low)
|
if reset = '0' then
|
if reset = '0' then
|
q1 := (others =>'0');
|
q1 := (others =>'0');
|
q2 := (others =>'0');
|
q2 := (others =>'0');
|
q3 := (others =>'0');
|
q3 := (others =>'0');
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
|
|
if WE = '1' and ( FULL = '0') then
|
if WE = '1' and ( FULL = '0') then
|
q1 := q1 + 1;
|
q1 := q1 + 1;
|
q3 := q3 +1;
|
q3 := q3 +1;
|
else
|
else
|
q1 := q1;
|
q1 := q1;
|
q3 := q3;
|
q3 := q3;
|
|
|
end if;
|
end if;
|
|
|
if RE = '1' and ( EMPTY = '0') then
|
if RE = '1' and ( EMPTY = '0') then
|
q2 := q2 + 1;
|
q2 := q2 + 1;
|
q3 := q3 -1;
|
q3 := q3 -1;
|
else
|
else
|
q2 := q2;
|
q2 := q2;
|
q3 := q3;
|
q3 := q3;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
R_ADD <= q2;
|
R_ADD <= q2;
|
W_ADD <= q1;
|
W_ADD <= q1;
|
D_ADD <= q3;
|
D_ADD <= q3;
|
|
|
end process ADD_gen;
|
end process ADD_gen;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
|
FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
|
EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0';
|
EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0';
|
HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0';
|
HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0';
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
|
end FIFO_v3;
|
end FIFO_v3;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
-- This arch was synthesized by webfitter
|
-- This arch was synthesized by webfitter
|
-- It is the same as fifo_v1 but
|
-- It is the same as fifo_v1 but
|
-- 1. address variables was changed to signals
|
-- 1. address variables was changed to signals
|
-- 2. else statement was removed from process sync_data
|
-- 2. else statement was removed from process sync_data
|
-- 3. address-width was changed to 3 instead of 8
|
-- 3. address-width was changed to 3 instead of 8
|
-- Input data _is_ latched
|
-- Input data _is_ latched
|
|
|
library ieee;
|
library ieee;
|
-- numeric package genertes compile error by webfitter compiler
|
-- numeric package genertes compile error by webfitter compiler
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
USE ieee.std_logic_signed.ALL;
|
USE ieee.std_logic_signed.ALL;
|
USE ieee.std_logic_arith.ALL;
|
USE ieee.std_logic_arith.ALL;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- purpose: FIFO Architecture
|
-- purpose: FIFO Architecture
|
architecture FIFO_v4 of FIFO is
|
architecture FIFO_v4 of FIFO is
|
|
|
-- constant values
|
-- constant values
|
constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
|
constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
|
constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
|
constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
|
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
|
|
|
|
signal Data_in_del : std_logic_vector(WIDTH - 1 downto 0); -- delayed Data in
|
signal Data_in_del : std_logic_vector(WIDTH - 1 downto 0); -- delayed Data in
|
|
|
|
|
signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
|
signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
|
signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
|
signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
|
signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address
|
signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address
|
|
|
signal REN_INT : std_logic; -- Internal Read Enable
|
signal REN_INT : std_logic; -- Internal Read Enable
|
signal WEN_INT : std_logic; -- Internal Write Enable
|
signal WEN_INT : std_logic; -- Internal Write Enable
|
|
|
component dpmem
|
component dpmem
|
generic (ADD_WIDTH : integer := 8;
|
generic (ADD_WIDTH : integer := 8;
|
WIDTH : integer := 8 );
|
WIDTH : integer := 8 );
|
|
|
port (clk : in std_logic;
|
port (clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_out : out std_logic_vector(WIDTH - 1 downto 0 );
|
data_out : out std_logic_vector(WIDTH - 1 downto 0 );
|
WR : in std_logic;
|
WR : in std_logic;
|
RE : in std_logic);
|
RE : in std_logic);
|
end component;
|
end component;
|
|
|
|
|
|
|
begin -- FIFO_v4
|
begin -- FIFO_v4
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
memcore: dpmem
|
memcore: dpmem
|
generic map (WIDTH => 8,
|
generic map (WIDTH => 8,
|
ADD_WIDTH =>8)
|
ADD_WIDTH =>8)
|
port map (clk => clk,
|
port map (clk => clk,
|
reset => reset,
|
reset => reset,
|
w_add => w_add,
|
w_add => w_add,
|
r_add => r_add,
|
r_add => r_add,
|
Data_in => data_in_del,
|
Data_in => data_in_del,
|
data_out => data_out,
|
data_out => data_out,
|
wr => wen_int,
|
wr => wen_int,
|
re => ren_int);
|
re => ren_int);
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
Sync_data: process(clk,reset)
|
Sync_data: process(clk,reset)
|
begin -- process Sync_data
|
begin -- process Sync_data
|
if reset ='0' then
|
if reset ='0' then
|
data_in_del <= (others =>'0');
|
data_in_del <= (others =>'0');
|
|
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
data_in_del <= data_in;
|
data_in_del <= data_in;
|
|
|
-- else statemnet was removed due to error (hdl
|
-- else statemnet was removed due to error (hdl
|
--
|
--
|
end if;
|
end if;
|
|
|
|
|
end process Sync_data;
|
end process Sync_data;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
|
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
|
|
|
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
|
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
|
Add_gen: process(clk,reset)
|
Add_gen: process(clk,reset)
|
-- The variables was replaced by add signals
|
-- The variables was replaced by add signals
|
|
|
begin -- process ADD_gen
|
begin -- process ADD_gen
|
|
|
-- activities triggered by asynchronous reset (active low)
|
-- activities triggered by asynchronous reset (active low)
|
if reset = '0' then
|
if reset = '0' then
|
W_ADD <= (others =>'0');
|
W_ADD <= (others =>'0');
|
R_ADD <= (others =>'0');
|
R_ADD <= (others =>'0');
|
D_ADD <= (others =>'0');
|
D_ADD <= (others =>'0');
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
|
|
if WE = '1' and ( FULL = '0') then
|
if WE = '1' and ( FULL = '0') then
|
W_ADD <= W_ADD + 1;
|
W_ADD <= W_ADD + 1;
|
D_ADD <= D_ADD +1;
|
D_ADD <= D_ADD +1;
|
-- else
|
-- else
|
-- W_ADD <= W_ADD;
|
-- W_ADD <= W_ADD;
|
-- D_ADD <= D_ADD;
|
-- D_ADD <= D_ADD;
|
|
|
end if;
|
end if;
|
|
|
if RE = '1' and ( EMPTY = '0') then
|
if RE = '1' and ( EMPTY = '0') then
|
R_ADD <= R_ADD + 1;
|
R_ADD <= R_ADD + 1;
|
D_ADD <= D_ADD -1;
|
D_ADD <= D_ADD -1;
|
-- else
|
-- else
|
-- R_ADD <= R_ADD;
|
-- R_ADD <= R_ADD;
|
-- D_ADD <= D_ADD;
|
-- D_ADD <= D_ADD;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
|
|
end process ADD_gen;
|
end process ADD_gen;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
|
FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
|
EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0';
|
EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0';
|
HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0';
|
HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0';
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
|
|
|
end FIFO_v4;
|
end FIFO_v4;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
-- synthesized using webfitter
|
-- synthesized using webfitter
|
-- Input data is _NOT_ latched
|
-- Input data is _NOT_ latched
|
-- The same as fifo_v3 but without the use of the variables in add_gen process
|
-- The same as fifo_v3 but without the use of the variables in add_gen process
|
-- else case in add_gen "RE and WE" was removed
|
-- else case in add_gen "RE and WE" was removed
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
--use ieee.numeric_std.all;
|
--use ieee.numeric_std.all;
|
USE ieee.std_logic_signed.ALL;
|
USE ieee.std_logic_signed.ALL;
|
USE ieee.std_logic_arith.ALL;
|
USE ieee.std_logic_arith.ALL;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- purpose: FIFO Architecture
|
-- purpose: FIFO Architecture
|
architecture FIFO_v5 of FIFO is
|
architecture FIFO_v5 of FIFO is
|
|
|
-- constant values
|
-- constant values
|
constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
|
constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
|
constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
|
constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
|
|
|
|
signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
|
signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
|
signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
|
signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
|
signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address
|
signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address
|
|
|
signal REN_INT : std_logic; -- Internal Read Enable
|
signal REN_INT : std_logic; -- Internal Read Enable
|
signal WEN_INT : std_logic; -- Internal Write Enable
|
signal WEN_INT : std_logic; -- Internal Write Enable
|
|
|
component dpmem
|
component dpmem
|
generic (ADD_WIDTH : integer := 8;
|
generic (ADD_WIDTH : integer := 8;
|
WIDTH : integer := 8 );
|
WIDTH : integer := 8 );
|
|
|
port (clk : in std_logic;
|
port (clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_out : out std_logic_vector(WIDTH - 1 downto 0 );
|
data_out : out std_logic_vector(WIDTH - 1 downto 0 );
|
WR : in std_logic;
|
WR : in std_logic;
|
RE : in std_logic);
|
RE : in std_logic);
|
end component;
|
end component;
|
|
|
|
|
|
|
begin -- FIFO_v5
|
begin -- FIFO_v5
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
memcore: dpmem
|
memcore: dpmem
|
generic map (WIDTH => 8,
|
generic map (WIDTH => 8,
|
ADD_WIDTH =>8)
|
ADD_WIDTH =>8)
|
port map (clk => clk,
|
port map (clk => clk,
|
reset => reset,
|
reset => reset,
|
w_add => w_add,
|
w_add => w_add,
|
r_add => r_add,
|
r_add => r_add,
|
Data_in => data_in,
|
Data_in => data_in,
|
data_out => data_out,
|
data_out => data_out,
|
wr => wen_int,
|
wr => wen_int,
|
re => ren_int);
|
re => ren_int);
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
|
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
|
|
|
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
|
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
Add_gen: process(clk,reset)
|
Add_gen: process(clk,reset)
|
|
|
begin -- process ADD_gen
|
begin -- process ADD_gen
|
|
|
-- activities triggered by asynchronous reset (active low)
|
-- activities triggered by asynchronous reset (active low)
|
if reset = '0' then
|
if reset = '0' then
|
W_ADD <= (others =>'0');
|
W_ADD <= (others =>'0');
|
R_ADD <= (others =>'0');
|
R_ADD <= (others =>'0');
|
D_ADD <= (others =>'0');
|
D_ADD <= (others =>'0');
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
|
|
if WE = '1' and ( FULL = '0') then
|
if WE = '1' and ( FULL = '0') then
|
W_ADD <= W_ADD + 1;
|
W_ADD <= W_ADD + 1;
|
D_ADD <= D_ADD +1;
|
D_ADD <= D_ADD +1;
|
-- else
|
-- else
|
-- W_ADD <= W_ADD;
|
-- W_ADD <= W_ADD;
|
-- D_ADD <= D_ADD;
|
-- D_ADD <= D_ADD;
|
|
|
end if;
|
end if;
|
|
|
if RE = '1' and ( EMPTY = '0') then
|
if RE = '1' and ( EMPTY = '0') then
|
R_ADD <= R_ADD + 1;
|
R_ADD <= R_ADD + 1;
|
D_ADD <= D_ADD -1;
|
D_ADD <= D_ADD -1;
|
-- else
|
-- else
|
-- R_ADD <= R_ADD;
|
-- R_ADD <= R_ADD;
|
-- D_ADD <= D_ADD;
|
-- D_ADD <= D_ADD;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
-- R_ADD <= q2;
|
-- R_ADD <= q2;
|
-- W_ADD <= q1;
|
-- W_ADD <= q1;
|
-- D_ADD <= q3;
|
-- D_ADD <= q3;
|
|
|
end process ADD_gen;
|
end process ADD_gen;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
|
FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
|
EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0';
|
EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0';
|
HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0';
|
HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0';
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
|
end FIFO_v5;
|
end FIFO_v5;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
-- Exactly teh same as FIFO_v5 but ieee.numeric_std.all is used
|
-- Exactly teh same as FIFO_v5 but ieee.numeric_std.all is used
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
--USE ieee.std_logic_signed.ALL;
|
--USE ieee.std_logic_signed.ALL;
|
--USE ieee.std_logic_arith.ALL;
|
--USE ieee.std_logic_arith.ALL;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- purpose: FIFO Architecture
|
-- purpose: FIFO Architecture
|
architecture FIFO_v6 of FIFO is
|
architecture FIFO_v6 of FIFO is
|
|
|
-- constant values
|
-- constant values
|
constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
|
constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
|
constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
|
constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
|
|
signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
|
signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
|
signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
|
signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
|
signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address
|
signal D_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Diff Address
|
|
|
signal REN_INT : std_logic; -- Internal Read Enable
|
signal REN_INT : std_logic; -- Internal Read Enable
|
signal WEN_INT : std_logic; -- Internal Write Enable
|
signal WEN_INT : std_logic; -- Internal Write Enable
|
|
|
component dpmem
|
component dpmem
|
generic (ADD_WIDTH : integer := 8;
|
generic (ADD_WIDTH : integer := 8;
|
WIDTH : integer := 8 );
|
WIDTH : integer := 8 );
|
|
|
port (clk : in std_logic;
|
port (clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_out : out std_logic_vector(WIDTH - 1 downto 0 );
|
data_out : out std_logic_vector(WIDTH - 1 downto 0 );
|
WR : in std_logic;
|
WR : in std_logic;
|
RE : in std_logic);
|
RE : in std_logic);
|
end component;
|
end component;
|
|
|
|
|
|
|
begin -- FIFO_v6
|
begin -- FIFO_v6
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
memcore: dpmem
|
memcore: dpmem
|
generic map (WIDTH => 8,
|
generic map (WIDTH => 8,
|
ADD_WIDTH =>8)
|
ADD_WIDTH =>8)
|
port map (clk => clk,
|
port map (clk => clk,
|
reset => reset,
|
reset => reset,
|
w_add => w_add,
|
w_add => w_add,
|
r_add => r_add,
|
r_add => r_add,
|
Data_in => data_in,
|
Data_in => data_in,
|
data_out => data_out,
|
data_out => data_out,
|
wr => wen_int,
|
wr => wen_int,
|
re => ren_int);
|
re => ren_int);
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
|
wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';
|
|
|
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
|
ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
Add_gen: process(clk,reset)
|
Add_gen: process(clk,reset)
|
|
|
begin -- process ADD_gen
|
begin -- process ADD_gen
|
|
|
-- activities triggered by asynchronous reset (active low)
|
-- activities triggered by asynchronous reset (active low)
|
if reset = '0' then
|
if reset = '0' then
|
W_ADD <= (others =>'0');
|
W_ADD <= (others =>'0');
|
R_ADD <= (others =>'0');
|
R_ADD <= (others =>'0');
|
D_ADD <= (others =>'0');
|
D_ADD <= (others =>'0');
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
|
|
if WE = '1' and ( FULL = '0') then
|
if WE = '1' and ( FULL = '0') then
|
W_ADD <= W_ADD + 1;
|
W_ADD <= W_ADD + 1;
|
D_ADD <= D_ADD +1;
|
D_ADD <= D_ADD +1;
|
-- else
|
-- else
|
-- W_ADD <= W_ADD;
|
-- W_ADD <= W_ADD;
|
-- D_ADD <= D_ADD;
|
-- D_ADD <= D_ADD;
|
|
|
end if;
|
end if;
|
|
|
if RE = '1' and ( EMPTY = '0') then
|
if RE = '1' and ( EMPTY = '0') then
|
R_ADD <= R_ADD + 1;
|
R_ADD <= R_ADD + 1;
|
D_ADD <= D_ADD -1;
|
D_ADD <= D_ADD -1;
|
-- else
|
-- else
|
-- R_ADD <= R_ADD;
|
-- R_ADD <= R_ADD;
|
-- D_ADD <= D_ADD;
|
-- D_ADD <= D_ADD;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
-- R_ADD <= q2;
|
-- R_ADD <= q2;
|
-- W_ADD <= q1;
|
-- W_ADD <= q1;
|
-- D_ADD <= q3;
|
-- D_ADD <= q3;
|
|
|
end process ADD_gen;
|
end process ADD_gen;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
|
FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
|
EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0';
|
EMPTY <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MIN_ADDR) else '0';
|
HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0';
|
HALF_FULL <= '1'when (D_ADD(ADD_WIDTH - 1 downto 0) > HALF_ADDR) else '0';
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
|
end FIFO_v6;
|
end FIFO_v6;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
-- 1- Synchronous FIFO
|
-- 1- Synchronous FIFO
|
-- 2- Read & write are synchronized to the same clock
|
-- 2- Read & write are synchronized to the same clock
|
-- 3- Input data should be stable one clock after Wr
|
-- 3- Input data should be stable one clock after Wr
|
-- 4-
|
-- 4-
|
|
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- purpose: FIFO Architecture
|
-- purpose: FIFO Architecture
|
architecture FIFO_v7 of FIFO is
|
architecture FIFO_v7 of FIFO is
|
|
|
-- constant values
|
-- constant values
|
constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
|
constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
|
constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
|
constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := '0' & (MAX_ADDR'range => '1');
|
|
|
|
|
-- Internal signals
|
-- Internal signals
|
signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
|
signal R_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Read Address
|
signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
|
signal W_ADD : std_logic_vector(ADD_WIDTH - 1 downto 0); -- Write Address
|
|
|
signal REN_INT : std_logic; -- Internal Read Enable
|
signal REN_INT : std_logic; -- Internal Read Enable
|
signal WEN_INT : std_logic; -- Internal Write Enable
|
signal WEN_INT : std_logic; -- Internal Write Enable
|
|
|
-- signal int_full : std_logic;
|
-- signal int_full : std_logic;
|
-- signal int_empty : std_logic;
|
-- signal int_empty : std_logic;
|
|
|
signal datainREG : std_logic_vector(WIDTH - 1 downto 0); -- Data in regiester
|
signal datainREG : std_logic_vector(WIDTH - 1 downto 0); -- Data in regiester
|
signal dataoutREG : std_logic_vector(WIDTH - 1 downto 0); -- Data out regiester
|
signal dataoutREG : std_logic_vector(WIDTH - 1 downto 0); -- Data out regiester
|
|
|
|
|
component dpmem
|
component dpmem
|
generic (ADD_WIDTH : integer := 4;
|
generic (ADD_WIDTH : integer := 4;
|
WIDTH : integer := 8 );
|
WIDTH : integer := 8 );
|
|
|
port (clk : in std_logic;
|
port (clk : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
w_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
r_add : in std_logic_vector(ADD_WIDTH -1 downto 0 );
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_in : in std_logic_vector(WIDTH - 1 downto 0);
|
data_out : out std_logic_vector(WIDTH - 1 downto 0 );
|
data_out : out std_logic_vector(WIDTH - 1 downto 0 );
|
WR : in std_logic;
|
WR : in std_logic;
|
RE : in std_logic);
|
RE : in std_logic);
|
end component;
|
end component;
|
|
|
|
|
|
|
begin -- FIFO_v7
|
begin -- FIFO_v7
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
memcore: dpmem
|
memcore: dpmem
|
generic map (WIDTH => 8,
|
generic map (WIDTH => 8,
|
ADD_WIDTH =>4)
|
ADD_WIDTH =>4)
|
port map (clk => clk,
|
port map (clk => clk,
|
reset => reset,
|
reset => reset,
|
w_add => w_add,
|
w_add => w_add,
|
r_add => r_add,
|
r_add => r_add,
|
Data_in => datainREG,
|
Data_in => datainREG,
|
data_out => dataoutREG,
|
data_out => dataoutREG,
|
wr => wen_int,
|
wr => wen_int,
|
re => re);
|
re => re);
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
Add_gen: process(clk,reset)
|
Add_gen: process(clk,reset)
|
|
|
variable full_var : std_logic;
|
variable full_var : std_logic;
|
variable empty_var : std_logic;
|
variable empty_var : std_logic;
|
variable half_full_var : std_logic;
|
variable half_full_var : std_logic;
|
|
|
variable W_ADD_old : std_logic_vector(ADD_WIDTH -1 downto 0);
|
variable W_ADD_old : std_logic_vector(ADD_WIDTH -1 downto 0);
|
|
|
|
|
variable D_ADD : std_logic_vector(add_width -1 downto 0);
|
variable D_ADD : std_logic_vector(add_width -1 downto 0);
|
|
|
|
|
begin -- process ADD_gen
|
begin -- process ADD_gen
|
|
|
-- activities triggered by asynchronous reset (active low)
|
-- activities triggered by asynchronous reset (active low)
|
if reset = '0' then
|
if reset = '0' then
|
W_ADD <= (others =>'0');
|
W_ADD <= (others =>'0');
|
R_ADD <= (others =>'0');
|
R_ADD <= (others =>'0');
|
D_ADD := (others => '0');
|
D_ADD := (others => '0');
|
|
|
W_ADD_old := (others => '0');
|
W_ADD_old := (others => '0');
|
|
|
full_var := '0';
|
full_var := '0';
|
empty_var := '1';
|
empty_var := '1';
|
half_full_var := '0';
|
half_full_var := '0';
|
|
|
FULL <= full_var;
|
FULL <= full_var;
|
EMPTY <= empty_var;
|
EMPTY <= empty_var;
|
HALF_FULL <= half_full_var;
|
HALF_FULL <= half_full_var;
|
|
|
ren_int <= '0';
|
ren_int <= '0';
|
wen_int <= '0';
|
wen_int <= '0';
|
|
|
datainreg <= (others => '1');
|
datainreg <= (others => '1');
|
data_out <= (others => '1');
|
data_out <= (others => '1');
|
|
|
-- activities triggered by rising edge of clock
|
-- activities triggered by rising edge of clock
|
elsif clk'event and clk = '1' then
|
elsif clk'event and clk = '1' then
|
|
|
if ren_int = '1' and wen_int = '1' and empty_var = '1' then
|
if ren_int = '1' and wen_int = '1' and empty_var = '1' then
|
data_out <= data_in;
|
data_out <= data_in;
|
|
|
else
|
else
|
|
|
datainREG <= data_in;
|
datainREG <= data_in;
|
|
|
if ren_int = '1' then
|
if ren_int = '1' then
|
|
|
data_out <= dataoutREG;
|
data_out <= dataoutREG;
|
else
|
else
|
data_out <= (others => '1');
|
data_out <= (others => '1');
|
end if;
|
end if;
|
|
|
|
|
|
|
W_ADD <= W_ADD_old;
|
W_ADD <= W_ADD_old;
|
|
|
if WE = '1' then
|
if WE = '1' then
|
if FULL_var = '0' then
|
if FULL_var = '0' then
|
W_ADD_old := W_ADD_old + 1;
|
W_ADD_old := W_ADD_old + 1;
|
D_ADD := D_ADD +1;
|
D_ADD := D_ADD +1;
|
wen_int <= '1';
|
wen_int <= '1';
|
|
|
else
|
else
|
wen_int <= '0';
|
wen_int <= '0';
|
|
|
end if;
|
end if;
|
|
|
else
|
else
|
wen_int <= '0';
|
wen_int <= '0';
|
|
|
end if;
|
end if;
|
|
|
|
|
if RE = '1' then
|
if RE = '1' then
|
if EMPTY_var = '0' then
|
if EMPTY_var = '0' then
|
R_ADD <= R_ADD + 1;
|
R_ADD <= R_ADD + 1;
|
D_ADD := D_ADD -1;
|
D_ADD := D_ADD -1;
|
ren_int <= '1';
|
ren_int <= '1';
|
else
|
else
|
ren_int <= '0';
|
ren_int <= '0';
|
|
|
end if;
|
end if;
|
|
|
else
|
else
|
ren_int <= '0';
|
ren_int <= '0';
|
end if;
|
end if;
|
|
|
|
|
full_var := '0';
|
full_var := '0';
|
empty_var := '0';
|
empty_var := '0';
|
half_full_var := '0';
|
half_full_var := '0';
|
|
|
|
|
if D_ADD = MAX_ADDR then
|
if D_ADD = MAX_ADDR then
|
full_var := '1';
|
full_var := '1';
|
|
|
end if;
|
end if;
|
|
|
if D_ADD = MIN_ADDR then
|
if D_ADD = MIN_ADDR then
|
empty_var := '1';
|
empty_var := '1';
|
|
|
end if;
|
end if;
|
|
|
if D_ADD(ADD_WIDTH -1) = '1' then
|
if D_ADD(ADD_WIDTH -1) = '1' then
|
half_full_var := '1';
|
half_full_var := '1';
|
|
|
end if;
|
end if;
|
|
|
FULL <= full_var;
|
FULL <= full_var;
|
EMPTY <= empty_var;
|
EMPTY <= empty_var;
|
HALF_FULL <= half_full_var;
|
HALF_FULL <= half_full_var;
|
|
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
end process ADD_gen;
|
end process ADD_gen;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
|
end FIFO_v7;
|
end FIFO_v7;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
|
|
configuration fifo_conf of fifo is
|
configuration fifo_conf of fifo is
|
for fifo_v1
|
for fifo_v1
|
for memcore:dpmem
|
for memcore:dpmem
|
use entity work.dpmem(dpmem_v3);
|
use entity work.dpmem(dpmem_v3);
|
end for;
|
end for;
|
end for;
|
end for;
|
|
|
end fifo_conf;
|
end fifo_conf;
|
|
|
|
|
|
|
