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echo Copyright Jamil Khatib 1999
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echo Copyright Jamil Khatib 1999
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echo
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echo
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echo This test vector file is an open design, you can redistribute it and/or
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echo This test vector file is an open design, you can redistribute it and/or
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echo modify it under the terms of the Openip Hardware General Public
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echo modify it under the terms of the Openip Hardware General Public
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echo License as as published by the OpenIP organization and any
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echo License as as published by the OpenIP organization and any
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echo coming versions of this license.
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echo coming versions of this license.
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echo You can check the draft license at
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echo You can check the draft license at
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echo http://www.openip.org/oc/license.html
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echo http://www.openip.org/oc/license.html
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echo
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echo
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echo
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echo
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echo Creator : Jamil Khatib
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echo Creator : Jamil Khatib
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echo Date 14/5/99
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echo Date 14/5/99
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echo
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echo
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echo version 0.19990704
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echo version 0.19990704
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echo contact me at khatib@ieee.org
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echo contact me at khatib@ieee.org
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view source
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view source
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view signals
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view signals
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view wave
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view wave
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add wave *
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add wave *
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#init clk
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#init clk
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force clk 1 10, 0 20 -r 20
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force clk 1 10, 0 20 -r 20
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# init reset
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# init reset
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force reset 1 0
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force reset 1 0
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#No read nor write
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#No read nor write
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force data_in 00000000 0
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force data_in 00000000 0
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force wr 0 0
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force wr 0 0
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force re 0 0
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force re 0 0
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force R_add 00000000 0
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force R_add 00000000 0
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force W_add 00000000 0
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force W_add 00000000 0
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run 40
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run 40
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# write only cycles
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# write only cycles
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force data_in 00000000 0
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force data_in 00000000 0
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force wr 1 0
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force wr 1 0
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force W_add 00000000 0
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force W_add 00000000 0
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run 20
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run 20
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force data_in 00000001 0
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force data_in 00000001 0
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force wr 1 0
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force wr 1 0
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force W_add 00000001 0
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force W_add 00000001 0
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run 20
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run 20
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force data_in 00000011 0
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force data_in 00000011 0
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force wr 1 0
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force wr 1 0
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force W_add 00000010 0
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force W_add 00000010 0
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run 20
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run 20
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# Read only cycles
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# Read only cycles
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force data_in 00000000 0
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force data_in 00000000 0
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force wr 0 0
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force wr 0 0
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force re 1 0
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force re 1 0
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force R_add 00000000 0
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force R_add 00000000 0
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run 20
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run 20
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force re 1 0
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force re 1 0
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force R_add 00000001 0
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force R_add 00000001 0
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run 20
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run 20
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force re 1 0
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force re 1 0
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force R_add 00000010 0
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force R_add 00000010 0
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run 20
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run 20
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# Read and write from different addresses
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# Read and write from different addresses
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force data_in 00000111 0
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force data_in 00000111 0
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force W_add 00000011 0
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force W_add 00000011 0
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force R_add 00000001 0
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force R_add 00000001 0
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force wr 1 0
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force wr 1 0
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force re 1 0
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force re 1 0
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run 20
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run 20
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# Read and write from different addresses
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# Read and write from different addresses
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force data_in 00001111 0
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force data_in 00001111 0
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force W_add 00000100 0
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force W_add 00000100 0
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force R_add 00000011 0
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force R_add 00000011 0
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force wr 1 0
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force wr 1 0
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force re 1 0
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force re 1 0
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run 20
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run 20
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# Read and Write from the same address
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# Read and Write from the same address
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force data_in 00000000 0
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force data_in 00000000 0
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force W_add 00000010 0
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force W_add 00000010 0
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force R_add 00000010 0
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force R_add 00000010 0
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force wr 1 0
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force wr 1 0
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force re 1 0
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force re 1 0
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run 20
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run 20
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force data_in 00000000 0
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force data_in 00000000 0
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force W_add 00000100 0
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force W_add 00000100 0
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force R_add 00000100 0
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force R_add 00000100 0
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force wr 1 0
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force wr 1 0
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force re 1 0
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force re 1 0
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run 20
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run 20
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# reset system during Operation
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# reset system during Operation
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run 10
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run 10
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force reset 0 0
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force reset 0 0
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force data_in 00000000 0
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force data_in 00000000 0
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force W_add 00000100 0
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force W_add 00000100 0
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force R_add 00000100 0
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force R_add 00000100 0
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force wr 1 0
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force wr 1 0
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force re 1 0
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force re 1 0
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run 20
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run 20
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force reset 1 0
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force reset 1 0
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force data_in 11111111 0
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force data_in 11111111 0
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force W_add 00000100 0
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force W_add 00000100 0
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force R_add 00000100 0
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force R_add 00000100 0
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force wr 1 0
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force wr 1 0
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force re 1 0
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force re 1 0
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run 20
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run 20
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