-- $Id: input.vhdl,v 1.2 2005-12-23 04:27:00 arif_endro Exp $
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-- $Id: input.vhdl,v 1.2 2005-12-23 04:27:00 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Input
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-- Title : Input
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-- Project : Mini AES 128
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-- Project : Mini AES 128
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : input.vhdl
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-- File : input.vhdl
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2005/12/03
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-- Created : 2005/12/03
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-- Last update :
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-- Last update :
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-- Simulators : ModelSim SE PLUS 6.0
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-- Simulators : ModelSim SE PLUS 6.0
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-- Synthesizers: ISE Xilinx 6.3i
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-- Synthesizers: ISE Xilinx 6.3i
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-- Target :
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-- Target :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description : Input stimuli file for test bench.
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-- Description : Input stimuli file for test bench.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (C) 2005 Arif E. Nugroho
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-- Copyright (C) 2005 Arif E. Nugroho
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- ASSOCIATED DISCLAIMER.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_textio.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use std.textio.all;
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library std_developerskit;
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library std_developerskit;
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use std_developerskit.std_iopak.all; -- Function From_HexString
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use std_developerskit.std_iopak.all; -- Function From_HexString
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entity input is
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entity input is
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port (
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port (
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clock : out std_logic;
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clock : out std_logic;
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load : out std_logic;
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load : out std_logic;
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done : in std_logic;
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done : in std_logic;
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test_iteration : out integer;
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test_iteration : out integer;
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key_i_byte : out std_logic_vector (007 downto 000);
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key_i_byte : out std_logic_vector (007 downto 000);
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data_i_byte : out std_logic_vector (007 downto 000);
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data_i_byte : out std_logic_vector (007 downto 000);
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cipher_o_byte : out std_logic_vector (007 downto 000)
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cipher_o_byte : out std_logic_vector (007 downto 000)
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);
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);
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end input;
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end input;
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architecture test_bench of input is
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architecture test_bench of input is
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--
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--
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file in_file_ptr : text open read_mode is "../data/ecb_tbl.txt";
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file in_file_ptr : text open read_mode is "../data/ecb_tbl.txt";
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--
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--
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signal clock_int : std_logic := '0';
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signal clock_int : std_logic := '0';
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signal ct : std_logic_vector (127 downto 000);
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signal ct : std_logic_vector (127 downto 000);
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signal pt : std_logic_vector (127 downto 000);
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signal pt : std_logic_vector (127 downto 000);
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signal ky : std_logic_vector (127 downto 000);
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signal ky : std_logic_vector (127 downto 000);
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--
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--
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begin
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begin
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--
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--
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clock_int <= not(clock_int) after 1 ns;
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clock_int <= not(clock_int) after 1 ns;
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clock <= clock_int;
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clock <= clock_int;
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--
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--
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process
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process
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--
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--
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variable delay : time := 1 ns;
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variable delay : time := 1 ns;
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variable in_line : line;
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variable in_line : line;
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variable cipher_text : string ( 01 to 32 );
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variable cipher_text : string ( 01 to 32 );
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variable plain_text : string ( 01 to 32 );
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variable plain_text : string ( 01 to 32 );
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variable key : string ( 01 to 32 );
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variable key : string ( 01 to 32 );
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variable test : integer;
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variable test : integer;
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variable junk_test : string ( 01 to 02 );
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variable junk_test : string ( 01 to 02 );
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variable junk_plain_text : string ( 01 to 03 );
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variable junk_plain_text : string ( 01 to 03 );
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variable junk_cipher_text : string (01 to 03 );
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variable junk_cipher_text : string (01 to 03 );
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variable junk_key : string ( 01 to 04 );
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variable junk_key : string ( 01 to 04 );
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--
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--
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begin
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begin
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--
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--
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while not (endfile(in_file_ptr)) loop
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while not (endfile(in_file_ptr)) loop
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--
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--
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readline(in_file_ptr, in_line); -- blank lines
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readline(in_file_ptr, in_line); -- blank lines
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--
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--
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readline(in_file_ptr, in_line);
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readline(in_file_ptr, in_line);
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read(in_line, junk_test);
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read(in_line, junk_test);
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read(in_line, test);
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read(in_line, test);
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readline(in_file_ptr, in_line);
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readline(in_file_ptr, in_line);
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read(in_line, junk_key);
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read(in_line, junk_key);
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read(in_line, key);
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read(in_line, key);
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readline(in_file_ptr, in_line);
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readline(in_file_ptr, in_line);
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read(in_line, junk_plain_text);
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read(in_line, junk_plain_text);
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read(in_line, plain_text);
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read(in_line, plain_text);
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readline(in_file_ptr, in_line);
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readline(in_file_ptr, in_line);
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read(in_line, junk_cipher_text);
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read(in_line, junk_cipher_text);
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read(in_line, cipher_text);
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read(in_line, cipher_text);
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--
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--
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ky <= to_StdLogicVector(From_HexString(key( 01 to 32)));
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ky <= to_StdLogicVector(From_HexString(key( 01 to 32)));
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pt <= to_StdLogicVector(From_HexString(plain_text( 01 to 32 )));
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pt <= to_StdLogicVector(From_HexString(plain_text( 01 to 32 )));
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ct <= to_StdLogicVector(From_HexString(cipher_text( 01 to 32 )));
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ct <= to_StdLogicVector(From_HexString(cipher_text( 01 to 32 )));
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--
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--
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for a in 1 to key'length/2 loop
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for a in 1 to key'length/2 loop
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wait until rising_edge(clock_int);
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wait until rising_edge(clock_int);
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key_i_byte <= to_StdLogicVector(From_HexString(key(2*a-1 to 2*a)));
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key_i_byte <= to_StdLogicVector(From_HexString(key(2*a-1 to 2*a)));
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data_i_byte <= to_StdLogicVector(From_HexString(plain_text(2*a-1 to 2*a)));
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data_i_byte <= to_StdLogicVector(From_HexString(plain_text(2*a-1 to 2*a)));
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cipher_o_byte <= to_StdLogicVector(From_HexString(cipher_text(2*a-1 to 2*a)));
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cipher_o_byte <= to_StdLogicVector(From_HexString(cipher_text(2*a-1 to 2*a)));
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load <= '1';
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load <= '1';
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test_iteration <= test;
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test_iteration <= test;
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end loop;
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end loop;
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--
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--
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wait until rising_edge(clock_int);
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wait until rising_edge(clock_int);
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load <= '0';
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load <= '0';
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--
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--
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wait until falling_edge(done);
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wait until falling_edge(done);
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wait until rising_edge(clock_int);
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wait until rising_edge(clock_int);
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--
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--
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end loop;
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end loop;
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wait;
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wait;
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end process;
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end process;
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--
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--
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end test_bench;
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end test_bench;
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