-- $Id: modelsim_bench.vhdl,v 1.2 2005-12-23 04:27:00 arif_endro Exp $
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-- $Id: modelsim_bench.vhdl,v 1.2 2005-12-23 04:27:00 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : ModelSim bench
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-- Title : ModelSim bench
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-- Project : Mini AES 128
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-- Project : Mini AES 128
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : modelsim_bench.vhdl
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-- File : modelsim_bench.vhdl
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2005/12/03
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-- Created : 2005/12/03
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-- Last update :
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-- Last update :
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-- Simulators : ModelSim SE PLUS 6.0
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-- Simulators : ModelSim SE PLUS 6.0
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-- Synthesizers: ISE Xilinx 6.3i
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-- Synthesizers: ISE Xilinx 6.3i
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-- Target :
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-- Target :
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Description : Top module to connect all component in test bench.
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-- Description : Top module to connect all component in test bench.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Copyright (C) 2005 Arif E. Nugroho
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-- Copyright (C) 2005 Arif Endro Nugroho
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- ASSOCIATED DISCLAIMER.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity modelsim_bench is
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entity modelsim_bench is
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end modelsim_bench;
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end modelsim_bench;
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architecture structural of modelsim_bench is
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architecture structural of modelsim_bench is
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component mini_aes
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component mini_aes
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port (
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port (
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clock : in std_logic;
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clock : in std_logic;
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clear : in std_logic;
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clear : in std_logic;
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load_i : in std_logic;
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load_i : in std_logic;
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enc : in std_logic;
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enc : in std_logic;
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key_i : in std_logic_vector (007 downto 000);
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key_i : in std_logic_vector (007 downto 000);
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data_i : in std_logic_vector (007 downto 000);
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data_i : in std_logic_vector (007 downto 000);
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data_o : out std_logic_vector (007 downto 000);
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data_o : out std_logic_vector (007 downto 000);
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done_o : out std_logic
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done_o : out std_logic
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);
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);
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end component;
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end component;
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--
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--
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component input
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component input
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port (
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port (
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clock : out std_logic;
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clock : out std_logic;
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load : out std_logic;
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load : out std_logic;
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done : in std_logic;
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done : in std_logic;
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test_iteration : out integer;
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test_iteration : out integer;
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key_i_byte : out std_logic_vector (007 downto 000);
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key_i_byte : out std_logic_vector (007 downto 000);
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data_i_byte : out std_logic_vector (007 downto 000);
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data_i_byte : out std_logic_vector (007 downto 000);
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cipher_o_byte : out std_logic_vector (007 downto 000)
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cipher_o_byte : out std_logic_vector (007 downto 000)
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);
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);
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end component;
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end component;
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--
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--
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component output
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component output
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port (
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port (
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clock : in std_logic;
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clock : in std_logic;
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clear : in std_logic;
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clear : in std_logic;
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load : in std_logic;
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load : in std_logic;
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enc : in std_logic;
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enc : in std_logic;
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done : in std_logic;
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done : in std_logic;
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test_iteration : in integer;
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test_iteration : in integer;
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verifier : in std_logic_vector (007 downto 000);
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verifier : in std_logic_vector (007 downto 000);
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data_o : in std_logic_vector (007 downto 000)
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data_o : in std_logic_vector (007 downto 000)
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);
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);
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end component;
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end component;
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signal load_enc : std_logic;
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signal load_enc : std_logic;
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signal load_dec : std_logic;
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signal load_dec : std_logic;
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signal clock_enc : std_logic;
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signal clock_enc : std_logic;
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signal clock_dec : std_logic;
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signal clock_dec : std_logic;
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signal done_dec : std_logic;
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signal done_dec : std_logic;
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signal done_enc : std_logic;
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signal done_enc : std_logic;
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signal test_iteration_enc : integer;
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signal test_iteration_enc : integer;
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signal test_iteration_dec : integer;
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signal test_iteration_dec : integer;
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signal cipher_o_enc : std_logic_vector (007 downto 000);
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signal cipher_o_enc : std_logic_vector (007 downto 000);
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signal cipher_o_dec : std_logic_vector (007 downto 000);
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signal cipher_o_dec : std_logic_vector (007 downto 000);
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signal data_i_enc : std_logic_vector (007 downto 000);
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signal data_i_enc : std_logic_vector (007 downto 000);
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signal data_i_dec : std_logic_vector (007 downto 000);
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signal data_i_dec : std_logic_vector (007 downto 000);
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signal data_o_enc : std_logic_vector (007 downto 000);
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signal data_o_enc : std_logic_vector (007 downto 000);
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signal data_o_dec : std_logic_vector (007 downto 000);
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signal data_o_dec : std_logic_vector (007 downto 000);
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signal key_i_enc : std_logic_vector (007 downto 000);
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signal key_i_enc : std_logic_vector (007 downto 000);
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signal key_i_dec : std_logic_vector (007 downto 000);
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signal key_i_dec : std_logic_vector (007 downto 000);
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begin
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begin
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my_aes_enc : mini_aes
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my_aes_enc : mini_aes
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port map (
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port map (
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clock => clock_enc,
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clock => clock_enc,
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clear => '0',
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clear => '0',
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load_i => load_enc,
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load_i => load_enc,
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enc => '0',
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enc => '0',
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key_i => key_i_enc,
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key_i => key_i_enc,
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data_i => data_i_enc,
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data_i => data_i_enc,
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data_o => data_o_enc,
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data_o => data_o_enc,
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done_o => done_enc
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done_o => done_enc
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);
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);
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--
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--
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my_aes_dec : mini_aes
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my_aes_dec : mini_aes
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port map (
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port map (
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clock => clock_dec,
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clock => clock_dec,
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clear => '0',
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clear => '0',
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load_i => load_dec,
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load_i => load_dec,
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enc => '1',
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enc => '1',
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key_i => key_i_dec,
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key_i => key_i_dec,
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data_i => cipher_o_dec,
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data_i => cipher_o_dec,
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data_o => data_o_dec,
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data_o => data_o_dec,
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done_o => done_dec
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done_o => done_dec
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);
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);
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--
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--
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my_input_enc : input
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my_input_enc : input
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port map (
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port map (
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clock => clock_enc,
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clock => clock_enc,
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load => load_enc,
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load => load_enc,
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done => done_enc,
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done => done_enc,
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test_iteration => test_iteration_enc,
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test_iteration => test_iteration_enc,
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key_i_byte => key_i_enc,
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key_i_byte => key_i_enc,
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data_i_byte => data_i_enc,
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data_i_byte => data_i_enc,
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cipher_o_byte => cipher_o_enc
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cipher_o_byte => cipher_o_enc
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);
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);
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my_input_dec : input
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my_input_dec : input
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port map (
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port map (
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clock => clock_dec,
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clock => clock_dec,
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load => load_dec,
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load => load_dec,
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done => done_dec,
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done => done_dec,
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test_iteration => test_iteration_dec,
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test_iteration => test_iteration_dec,
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data_i_byte => data_i_dec,
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data_i_byte => data_i_dec,
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cipher_o_byte => cipher_o_dec,
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cipher_o_byte => cipher_o_dec,
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key_i_byte => key_i_dec
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key_i_byte => key_i_dec
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);
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);
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--
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--
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my_output_enc : output
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my_output_enc : output
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port map (
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port map (
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clock => clock_enc,
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clock => clock_enc,
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clear => '0',
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clear => '0',
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load => load_enc,
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load => load_enc,
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enc => '0',
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enc => '0',
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done => done_enc,
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done => done_enc,
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test_iteration => test_iteration_enc,
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test_iteration => test_iteration_enc,
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verifier => cipher_o_enc,
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verifier => cipher_o_enc,
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data_o => data_o_enc
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data_o => data_o_enc
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);
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);
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--
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--
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my_output_dec : output
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my_output_dec : output
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port map (
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port map (
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clock => clock_dec,
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clock => clock_dec,
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clear => '0',
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clear => '0',
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load => load_dec,
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load => load_dec,
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enc => '1',
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enc => '1',
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done => done_dec,
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done => done_dec,
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test_iteration => test_iteration_dec,
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test_iteration => test_iteration_dec,
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verifier => data_i_dec,
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verifier => data_i_dec,
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data_o => data_o_dec
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data_o => data_o_dec
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);
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);
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end structural;
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end structural;
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