-- $Id: folded_register.vhdl,v 1.1.1.1 2005-12-06 02:48:32 arif_endro Exp $
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-- ------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Folded register.
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-- Project : Mini AES 128
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-------------------------------------------------------------------------------
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-- File : folded_register.vhdl
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created : 2005/12/03
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-- Last update :
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-- Simulators : ModelSim SE PLUS 6.0
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-- Synthesizers: ISE Xilinx 6.3i
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-- Target :
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-------------------------------------------------------------------------------
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-- Description : Folded register manipulations for manipulating data.
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-------------------------------------------------------------------------------
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-- Copyright (C) 2005 Arif Endro Nugroho
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-- Copyright (C) 2005 Arif Endro Nugroho
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-------------------------------------------------------------------------------
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-- All rights reserved.
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--
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--
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- Redistribution and use in source and binary forms, with or without
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- modification, are permitted provided that the following conditions
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- are met:
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-- ASSOCIATED DISCLAIMER.
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--
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--
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-------------------------------------------------------------------------------
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-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- 3. The name of Arif Endro Nugroho may not be used to endorse or promote
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-- products derived from this software without specific prior written
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-- permission.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-------------------------------------------------------------------------------
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-- End Of License.
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-- ------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity folded_register is
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entity folded_register is
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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enc_i : in std_logic;
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enc_i : in std_logic;
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load_i : in std_logic;
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load_i : in std_logic;
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data_i : in std_logic_vector (127 downto 000);
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data_i : in std_logic_vector (127 downto 000);
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key_i : in std_logic_vector (127 downto 000);
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key_i : in std_logic_vector (127 downto 000);
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di_0_i : in std_logic_vector (007 downto 000);
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di_0_i : in std_logic_vector (007 downto 000);
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di_1_i : in std_logic_vector (007 downto 000);
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di_1_i : in std_logic_vector (007 downto 000);
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di_2_i : in std_logic_vector (007 downto 000);
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di_2_i : in std_logic_vector (007 downto 000);
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di_3_i : in std_logic_vector (007 downto 000);
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di_3_i : in std_logic_vector (007 downto 000);
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do_0_o : out std_logic_vector (007 downto 000);
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do_0_o : out std_logic_vector (007 downto 000);
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do_1_o : out std_logic_vector (007 downto 000);
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do_1_o : out std_logic_vector (007 downto 000);
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do_2_o : out std_logic_vector (007 downto 000);
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do_2_o : out std_logic_vector (007 downto 000);
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do_3_o : out std_logic_vector (007 downto 000)
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do_3_o : out std_logic_vector (007 downto 000)
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);
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);
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end folded_register;
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end folded_register;
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architecture data_flow of folded_register is
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architecture data_flow of folded_register is
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component counter2bit
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component counter2bit
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port (
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port (
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clock : in std_logic;
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clock : in std_logic;
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clear : in std_logic;
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clear : in std_logic;
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count : out std_logic_vector (1 downto 0)
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count : out std_logic_vector (1 downto 0)
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);
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);
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end component;
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end component;
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type fifo16x8 is array (00 to 15) of std_logic_vector (7 downto 0);
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type fifo16x8 is array (00 to 15) of std_logic_vector (7 downto 0);
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type addr4x4 is array (3 downto 0) of std_logic_vector (3 downto 0);
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type addr4x4 is array (3 downto 0) of std_logic_vector (3 downto 0);
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type addr4x8 is array (3 downto 0) of std_logic_vector (7 downto 0);
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type addr4x8 is array (3 downto 0) of std_logic_vector (7 downto 0);
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signal foldreg0 : fifo16x8 :=
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signal foldreg0 : fifo16x8 :=
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(
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(
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"
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);
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);
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--
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--
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signal foldreg1 : fifo16x8 :=
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signal foldreg1 : fifo16x8 :=
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(
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(
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"
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);
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);
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--
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--
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signal foldreg2 : fifo16x8 :=
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signal foldreg2 : fifo16x8 :=
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(
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(
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00"
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);
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);
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signal round0 : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );
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signal round0 : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );
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--
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--
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signal a_0_i : std_logic_vector (3 downto 0) := ( B"0000" );
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signal a_0_i : std_logic_vector (3 downto 0) := ( B"0000" );
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signal a_1_i : std_logic_vector (3 downto 0) := ( B"0000" );
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signal a_1_i : std_logic_vector (3 downto 0) := ( B"0000" );
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signal a_2_i : std_logic_vector (3 downto 0) := ( B"0000" );
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signal a_2_i : std_logic_vector (3 downto 0) := ( B"0000" );
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signal a_3_i : std_logic_vector (3 downto 0) := ( B"0000" );
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signal a_3_i : std_logic_vector (3 downto 0) := ( B"0000" );
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--
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--
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constant fifo_addr_cons : std_logic_vector (63 downto 00) := ( X"05AF_49E3_8D27_C16B" );
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constant fifo_addr_cons : std_logic_vector (63 downto 00) := ( X"05AF_49E3_8D27_C16B" );
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constant fifo_addr_cons_inv : std_logic_vector (63 downto 00) := ( X"0DA7_41EB_852F_C963" );
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constant fifo_addr_cons_inv : std_logic_vector (63 downto 00) := ( X"0DA7_41EB_852F_C963" );
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signal fifo_addr : std_logic_vector (63 downto 00) := ( X"0000_0000_0000_0000" );
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signal fifo_addr : std_logic_vector (63 downto 00) := ( X"0000_0000_0000_0000" );
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--
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--
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signal tmp : addr4x8 := ( X"00", X"00", X"00", X"00" );
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signal tmp : addr4x8 := ( X"00", X"00", X"00", X"00" );
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signal addr : addr4x4 := ( X"0", X"0", X"0", X"0" );
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signal addr : addr4x4 := ( X"0", X"0", X"0", X"0" );
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--
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--
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signal count : std_logic_vector (1 downto 0);
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signal count : std_logic_vector (1 downto 0);
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signal switch : std_logic := '0';
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signal switch : std_logic := '0';
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signal reg_i : std_logic := '0';
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signal reg_i : std_logic := '0';
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begin
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begin
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sect : counter2bit
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sect : counter2bit
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port map (
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port map (
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clock => clk_i,
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clock => clk_i,
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clear => load_i,
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clear => load_i,
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count => count
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count => count
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);
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);
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round0 <= data_i xor key_i;
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round0 <= data_i xor key_i;
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process(clk_i, load_i)
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process(clk_i, load_i)
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begin
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begin
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if (load_i = '1') then
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if (load_i = '1') then
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foldreg0 <= (
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foldreg0 <= (
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round0 (127 downto 120), round0 (119 downto 112), round0 (111 downto 104), round0 (103 downto 096),
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round0 (127 downto 120), round0 (119 downto 112), round0 (111 downto 104), round0 (103 downto 096),
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round0 (095 downto 088), round0 (087 downto 080), round0 (079 downto 072), round0 (071 downto 064),
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round0 (095 downto 088), round0 (087 downto 080), round0 (079 downto 072), round0 (071 downto 064),
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round0 (063 downto 056), round0 (055 downto 048), round0 (047 downto 040), round0 (039 downto 032),
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round0 (063 downto 056), round0 (055 downto 048), round0 (047 downto 040), round0 (039 downto 032),
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round0 (031 downto 024), round0 (023 downto 016), round0 (015 downto 008), round0 (007 downto 000)
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round0 (031 downto 024), round0 (023 downto 016), round0 (015 downto 008), round0 (007 downto 000)
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);
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);
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--
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--
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foldreg1 <= (
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foldreg1 <= (
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round0 (127 downto 120), round0 (119 downto 112), round0 (111 downto 104), round0 (103 downto 096),
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round0 (127 downto 120), round0 (119 downto 112), round0 (111 downto 104), round0 (103 downto 096),
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round0 (095 downto 088), round0 (087 downto 080), round0 (079 downto 072), round0 (071 downto 064),
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round0 (095 downto 088), round0 (087 downto 080), round0 (079 downto 072), round0 (071 downto 064),
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round0 (063 downto 056), round0 (055 downto 048), round0 (047 downto 040), round0 (039 downto 032),
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round0 (063 downto 056), round0 (055 downto 048), round0 (047 downto 040), round0 (039 downto 032),
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round0 (031 downto 024), round0 (023 downto 016), round0 (015 downto 008), round0 (007 downto 000)
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round0 (031 downto 024), round0 (023 downto 016), round0 (015 downto 008), round0 (007 downto 000)
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);
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);
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--
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--
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if (enc_i = '0') then
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if (enc_i = '0') then
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fifo_addr <= fifo_addr_cons;
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fifo_addr <= fifo_addr_cons;
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else
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else
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fifo_addr <= fifo_addr_cons_inv;
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fifo_addr <= fifo_addr_cons_inv;
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end if;
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end if;
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reg_i <= '0';
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reg_i <= '0';
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elsif (clk_i = '1' and clk_i'event) then
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elsif (clk_i = '1' and clk_i'event) then
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if (reg_i = '1') then
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if (reg_i = '1') then
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foldreg0 (00 to 11) <= ( foldreg0 (04 to 15) );
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foldreg0 (00 to 11) <= ( foldreg0 (04 to 15) );
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foldreg0 (12 to 15) <= ( di_0_i, di_1_i, di_2_i, di_3_i );
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foldreg0 (12 to 15) <= ( di_0_i, di_1_i, di_2_i, di_3_i );
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else
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else
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foldreg1 (00 to 11) <= ( foldreg1 (04 to 15) );
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foldreg1 (00 to 11) <= ( foldreg1 (04 to 15) );
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foldreg1 (12 to 15) <= ( di_0_i, di_1_i, di_2_i, di_3_i );
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foldreg1 (12 to 15) <= ( di_0_i, di_1_i, di_2_i, di_3_i );
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end if;
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end if;
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fifo_addr (63 downto 16) <= fifo_addr (47 downto 00);
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fifo_addr (63 downto 16) <= fifo_addr (47 downto 00);
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fifo_addr (15 downto 00) <= fifo_addr (63 downto 48);
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fifo_addr (15 downto 00) <= fifo_addr (63 downto 48);
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if (switch = '1') then
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if (switch = '1') then
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reg_i <= not(reg_i);
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reg_i <= not(reg_i);
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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a_0_i <= addr(0);
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a_0_i <= addr(0);
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a_1_i <= addr(1);
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a_1_i <= addr(1);
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a_2_i <= addr(2);
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a_2_i <= addr(2);
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a_3_i <= addr(3);
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a_3_i <= addr(3);
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--
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--
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foldreg2 (00 to 11) <= ( foldreg0 (04 to 15) ) when (reg_i = '1') else ( foldreg1 (04 to 15) );
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foldreg2 (00 to 11) <= ( foldreg0 (04 to 15) ) when (reg_i = '1') else ( foldreg1 (04 to 15) );
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foldreg2 (12 to 15) <= ( di_0_i, di_1_i, di_2_i, di_3_i );
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foldreg2 (12 to 15) <= ( di_0_i, di_1_i, di_2_i, di_3_i );
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--
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--
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switch <= (count(1)) and (count(0));
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switch <= (count(1)) and (count(0));
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--
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--
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addr(0) <= fifo_addr (51 downto 48) when ( load_i = '1' ) else fifo_addr (35 downto 32);
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addr(0) <= fifo_addr (51 downto 48) when ( load_i = '1' ) else fifo_addr (35 downto 32);
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addr(1) <= fifo_addr (55 downto 52) when ( load_i = '1' ) else fifo_addr (39 downto 36);
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addr(1) <= fifo_addr (55 downto 52) when ( load_i = '1' ) else fifo_addr (39 downto 36);
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addr(2) <= fifo_addr (59 downto 56) when ( load_i = '1' ) else fifo_addr (43 downto 40);
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addr(2) <= fifo_addr (59 downto 56) when ( load_i = '1' ) else fifo_addr (43 downto 40);
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addr(3) <= fifo_addr (63 downto 60) when ( load_i = '1' ) else fifo_addr (47 downto 44);
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addr(3) <= fifo_addr (63 downto 60) when ( load_i = '1' ) else fifo_addr (47 downto 44);
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--
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--
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tmp(0) <= foldreg1(conv_integer(a_0_i)) when ( reg_i = '1' ) else foldreg0(conv_integer(a_0_i));
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tmp(0) <= foldreg1(conv_integer(a_0_i)) when ( reg_i = '1' ) else foldreg0(conv_integer(a_0_i));
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tmp(1) <= foldreg1(conv_integer(a_1_i)) when ( reg_i = '1' ) else foldreg0(conv_integer(a_1_i));
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tmp(1) <= foldreg1(conv_integer(a_1_i)) when ( reg_i = '1' ) else foldreg0(conv_integer(a_1_i));
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tmp(2) <= foldreg1(conv_integer(a_2_i)) when ( reg_i = '1' ) else foldreg0(conv_integer(a_2_i));
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tmp(2) <= foldreg1(conv_integer(a_2_i)) when ( reg_i = '1' ) else foldreg0(conv_integer(a_2_i));
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tmp(3) <= foldreg1(conv_integer(a_3_i)) when ( reg_i = '1' ) else foldreg0(conv_integer(a_3_i));
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tmp(3) <= foldreg1(conv_integer(a_3_i)) when ( reg_i = '1' ) else foldreg0(conv_integer(a_3_i));
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--
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--
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do_0_o <= tmp(3) when ( switch = '0') else foldreg2(conv_integer(a_3_i));
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do_0_o <= tmp(3) when ( switch = '0') else foldreg2(conv_integer(a_3_i));
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do_1_o <= tmp(2) when ( switch = '0') else foldreg2(conv_integer(a_2_i));
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do_1_o <= tmp(2) when ( switch = '0') else foldreg2(conv_integer(a_2_i));
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do_2_o <= tmp(1) when ( switch = '0') else foldreg2(conv_integer(a_1_i));
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do_2_o <= tmp(1) when ( switch = '0') else foldreg2(conv_integer(a_1_i));
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do_3_o <= tmp(0) when ( switch = '0') else foldreg2(conv_integer(a_0_i));
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do_3_o <= tmp(0) when ( switch = '0') else foldreg2(conv_integer(a_0_i));
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end data_flow;
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end data_flow;
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