------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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-- --
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-- --
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-- Copyright (c) 2004, Hangouet Samuel --
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-- Copyright (c) 2004, Hangouet Samuel --
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-- , Jan Sebastien --
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-- , Jan Sebastien --
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-- , Mouton Louis-Marie --
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-- , Mouton Louis-Marie --
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-- , Schneider Olivier all rights reserved --
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-- , Schneider Olivier all rights reserved --
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-- --
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-- --
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-- This file is part of miniMIPS. --
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-- This file is part of miniMIPS. --
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-- --
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-- --
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-- miniMIPS is free software; you can redistribute it and/or modify --
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-- miniMIPS is free software; you can redistribute it and/or modify --
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-- it under the terms of the GNU Lesser General Public License as published by --
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-- it under the terms of the GNU Lesser General Public License as published by --
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-- the Free Software Foundation; either version 2.1 of the License, or --
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-- the Free Software Foundation; either version 2.1 of the License, or --
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-- (at your option) any later version. --
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-- (at your option) any later version. --
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-- --
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-- --
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-- miniMIPS is distributed in the hope that it will be useful, --
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-- miniMIPS is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU Lesser General Public License for more details. --
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-- GNU Lesser General Public License for more details. --
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-- --
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-- --
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-- You should have received a copy of the GNU Lesser General Public License --
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-- You should have received a copy of the GNU Lesser General Public License --
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-- along with miniMIPS; if not, write to the Free Software --
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-- along with miniMIPS; if not, write to the Free Software --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
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-- --
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-- --
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------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
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-- If you encountered any problem, please contact :
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-- If you encountered any problem, please contact :
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--
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--
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-- lmouton@enserg.fr
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-- lmouton@enserg.fr
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-- oschneid@enserg.fr
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-- oschneid@enserg.fr
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-- shangoue@enserg.fr
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-- shangoue@enserg.fr
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--
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--
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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library std;
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library std;
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use std.textio.all;
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use std.textio.all;
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library work;
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library work;
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use work.pack_mips.all;
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use work.pack_mips.all;
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entity sim_minimips is
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entity sim_minimips is
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end;
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end;
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architecture bench of sim_minimips is
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architecture bench of sim_minimips is
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component minimips is
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component minimips is
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port (
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port (
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clock : in std_logic;
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clock : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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ram_req : out std_logic;
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ram_req : out std_logic;
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ram_adr : out bus32;
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ram_adr : out bus32;
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ram_r_w : out std_logic;
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ram_r_w : out std_logic;
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ram_data : inout bus32;
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ram_data : inout bus32;
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ram_ack : in std_logic;
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ram_ack : in std_logic;
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it_mat : in std_logic
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it_mat : in std_logic
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);
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);
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end component;
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end component;
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component ram is
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component ram is
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generic (mem_size : natural := 256;
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generic (mem_size : natural := 256;
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latency : time := 10 ns);
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latency : time := 10 ns);
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port(
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port(
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req : in std_logic;
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req : in std_logic;
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adr : in bus32;
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adr : in bus32;
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data_inout : inout bus32;
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data_inout : inout bus32;
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r_w : in std_logic;
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r_w : in std_logic;
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ready : out std_logic
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ready : out std_logic
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);
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);
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end component;
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end component;
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component rom is
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component rom is
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generic (mem_size : natural := 256;
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generic (mem_size : natural := 256;
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start : natural := 0;
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start : natural := 0;
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latency : time := 10 ns);
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latency : time := 10 ns);
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port(
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port(
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adr : in bus32;
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adr : in bus32;
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donnee : out bus32;
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donnee : out bus32;
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ack : out std_logic;
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ack : out std_logic;
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load : in std_logic;
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load : in std_logic;
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fname : in string
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fname : in string
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);
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);
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end component;
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end component;
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signal clock : std_logic := '0';
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signal clock : std_logic := '0';
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signal reset : std_logic;
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signal reset : std_logic;
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signal it_mat : std_logic := '0';
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signal it_mat : std_logic := '0';
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-- Connexion with the code memory
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-- Connexion with the code memory
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signal load : std_logic;
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signal load : std_logic;
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signal fichier : string(1 to 7);
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signal fichier : string(1 to 7);
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-- Connexion with the Ram
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-- Connexion with the Ram
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signal ram_req : std_logic;
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signal ram_req : std_logic;
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signal ram_adr : bus32;
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signal ram_adr : bus32;
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signal ram_r_w : std_logic;
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signal ram_r_w : std_logic;
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signal ram_data : bus32;
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signal ram_data : bus32;
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signal ram_rdy : std_logic;
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signal ram_rdy : std_logic;
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begin
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begin
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U_minimips : minimips port map (
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U_minimips : minimips port map (
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clock => clock,
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clock => clock,
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reset => reset,
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reset => reset,
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ram_req => ram_req,
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ram_req => ram_req,
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ram_adr => ram_adr,
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ram_adr => ram_adr,
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ram_r_w => ram_r_w,
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ram_r_w => ram_r_w,
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ram_data => ram_data,
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ram_data => ram_data,
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ram_ack => ram_rdy,
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ram_ack => ram_rdy,
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it_mat => it_mat
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it_mat => it_mat
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);
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);
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U_ram : ram port map (
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U_ram : ram port map (
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req => ram_req,
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req => ram_req,
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adr => ram_adr,
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adr => ram_adr,
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data_inout => ram_data,
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data_inout => ram_data,
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r_w => ram_r_w,
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r_w => ram_r_w,
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ready => ram_rdy
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ready => ram_rdy
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);
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);
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U_rom : rom port map (
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U_rom : rom port map (
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adr => ram_adr,
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adr => ram_adr,
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donnee => ram_data,
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donnee => ram_data,
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ack => ram_rdy,
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ack => ram_rdy,
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load => load,
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load => load,
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fname => fichier
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fname => fichier
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);
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);
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clock <= not clock after 20 ns;
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clock <= not clock after 20 ns;
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reset <= '0', '1' after 5 ns, '0' after 70 ns;
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reset <= '0', '1' after 5 ns, '0' after 70 ns;
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ram_data <= (others => 'L');
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ram_data <= (others => 'L');
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process
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process
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variable command : line;
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variable command : line;
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variable nomfichier : string(1 to 3);
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variable nomfichier : string(1 to 3);
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begin
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begin
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write (output, "Enter the filename : ");
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write (output, "Enter the filename : ");
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readline(input, command);
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readline(input, command);
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read(command, nomfichier);
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read(command, nomfichier);
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fichier <= nomfichier & ".bin";
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fichier <= nomfichier & ".bin";
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load <= '1';
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load <= '1';
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wait;
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wait;
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end process;
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end process;
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-- Memory Mapping
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-- Memory Mapping
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-- 0000 - 00FF ROM
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-- 0000 - 00FF ROM
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process (ram_adr, ram_r_w, ram_data)
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process (ram_adr, ram_r_w, ram_data)
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begin -- Emulation of an I/O controller
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begin -- Emulation of an I/O controller
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ram_data <= (others => 'Z');
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ram_data <= (others => 'Z');
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case ram_adr is
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case ram_adr is
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when X"00001000" => -- declenche une lecture avec interruption
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when X"00001000" => -- program an interrupt after 1000ns
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it_mat <= '1' after 1000 ns;
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it_mat <= '1' after 1000 ns;
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ram_rdy <= '1' after 5 ns;
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ram_rdy <= '1' after 5 ns;
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when X"00001001" => -- fournit la donnee et lache l'it
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when X"00001001" => -- clear interrupt line on cpu
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it_mat <= '0';
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it_mat <= '0';
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ram_data <= X"FFFFFFFF";
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ram_data <= X"FFFFFFFF";
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ram_rdy <= '1' after 5 ns;
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ram_rdy <= '1' after 5 ns;
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when others => ram_rdy <= 'L';
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when others => ram_rdy <= 'L';
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end case;
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end case;
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end process;
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end process;
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end bench;
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end bench;
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