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Rev 15 Rev 26 
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MiniUART IP CoreSpecification


Author: Philippe Carton
Philippe.carton2@libertysurf.fr


Rev. 0.1
 HEURE \@ "MMMM j, aaaa" September 10, 2002
This page has been intentionally left blank
Revision History

Rev.DateAuthorDescription0.128/12/01Philippe CartonFirst Draft0.25/3/02Philippe CartonDetailed Baudrate tolerance section

Contents


 RENV Introduction \h  \* FUSIONFORMAT Introduction		 RENVOIPAGE Introduction \h 1

 RENV IOports \h  \* FUSIONFORMAT IO ports 		 RENVOIPAGE IOports \h 2

 RENV Clocks \h  \* FUSIONFORMAT Clocks 		 RENVOIPAGE Clocks
 \h 3

 RENV Registers \h  \* FUSIONFORMAT Registers 		 RENVOIPAGE Registers \h 4

 RENV Operation \h  \* FUSIONFORMAT Operation 		 RENVOIPAGE Operation \h 6

 RENV Architecture \h  \* FUSIONFORMAT Architecture 		 RENVOIPAGE Architecture \h 8
1
Introduction

This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core.
It works fine connected to the serial port of a PC for data exchange with custom electronic.
It was built in the perspective to be very small, but efficient. It had to fit in a small FPGA.
It is not suited to interface a modem as there is no control handshaking (CTS/RTS).
It integrate two separate clocks, one for wishbone bus, the other for bitstream generation. This has the advantage to let the user bring his own desired frequency for the baudrate.

Support:

WISHBONE interface in 8-bit data bus
Two clock: one for wishbone interface, one for RS232 bitstream generation
Baudrate divisor from 1 to 65536 (generic parameter set at integration time)

Does not support:
FIFO input/output
Control handshaking
2
IO ports

2.1 WISHBONE interface signals

PortWidthDirectionDescriptionWB_CLK_I1InputBlocks clock inputWB_RST_I1InputAsynchronous ResetWB_ADDR_I2InputUsed for register selectionWB_DAT_I8InputData inputWB_DAT_O8OutputData outputWB_WE_I1InputWrite or read cycle selectionWB_STB_I1InputSpecifies transfer cycleWB_ACK_O1OutputAcknowledge of a transfer
2.2 Other internal signals

PortWidthDirectionDescriptionIntTx_O1OutputTransmit InterruptIntRx_O1OutputReceive InterruptBR_CLK_I1OutputClock for serialisation/unserialisation
2.3 External (off-chip) connections

PortWidthDirectionDescriptionTxD_PAD_O1OutputThe serial output signalRxD_PAD_I1InputThe serial input signal
3
Clocks
Clocks table:

NameSourceRates (MHz)RemarksDescriptionMaxMinResolutionWB_CLK_IWishbone busLimited by target hostNoneWishbone clockBR_CLK_IUserNoneBaudrate clock4
Registers

4.1 Registers list

NameAddressWidthAccessDescriptionReceive buffer08RContain byte receivedTransmit buffer08WContain byte to transmitStatus18RReceive buffer full / Transmitter busyReserved28Reserved38
4.2 Status register

Bit #AccessDescription0RTransmitter buffer state = IntTx_O pin
	0  Busy. Cant accept incoming byte
	1  Accept a byte to transmit1RReceiver buffer state = IntRx_O pin
	0  Buffer empty
	1  Buffer contain a received byte
Reset Value: XXXXXX01b

5
Operation

The UART Operation is very basic :
Upon a write to the data input bus WB_DAT_I, the core will automatically serialise and emit the byte on the TxD_PAD_O. It will hold IntTx_O low as long as it cannot accept an incoming byte. Therefore a rising edge on IntTx_O can trigger the interrupt line of a microcontroller to emit another byte.
Upon reception of a bitstream on RxD_PAD_O, the core will unserialise the information and assert IntRx_O pin. This announce that the received byte can be read on the data output bus WB_DAT_O. As soon as the byte is read, IntRx_O is negated.

Wishbone bus
The core is 8 bit wishbone compatible. It doesnt use the WB_CYC_I pin as it will never insert wait states.

Initialization
The core doesnt need to be reset, as it is ready to use upon power on.
However, a synchronous assertion of WB_RST_I will abort any pending transmit / receive and will set the core in idle state.

Baudrate divisor
A generic VHDL parameter allow the user to introduce a divisor between BR_CLK_I clock and the bitstream frequency. In addition, the core insert a 4 divisor for sampling purpose for the receiver.

Thus:
	Baudrate = Freq(BR_CLK_I) / BRDIVISOR / 4

Where BRDIVISOR is the generic parameter.

To instanciate the component in a VHDL unit, write:

U1 : MiniUART
generic map (BRDIVISOR => 103)
port map (clk, rst, adr, ...);

for a division of 103.
Below are given some divisor values for common baudrates:

Baudrate tolerance
The receiver will accept a light variation between the expected baudrate and the effective bitstream baudrate that is:

Min freqNominal Baudrate -2.60%Max freqNominal Baudrate +5.90%
Equivalent in period :
Min periodNominal period -5.90%Max periodNominal period +2.60%
Going beyond this limits, the receiver will be unable to deserialise correctly.
6
Architecture

The block diagram of the core is given:

OpenCores        MiniUART core specifications     DATE  \* FUSIONFORMAT 10/09/02

LIENHYPERTEXTE "http://www.opencores.org/"www.opencores.org     Rev 0.1 Preliminary      PAGE   of  PAGESDESECTION2

LIENHYPERTEXTE "http://www.opencores.org/"www.opencores.org   Rev 0.1  PAGE ii 

LIENHYPERTEXTE "http://www.opencores.org/"www.opencores.org     Rev 0.1  PAGE 7 of  PAGESDESECTION8


Figure  SEQ Figure \* ARABE 1 - Block Diagram of the UART core

 INCORPORER Word.Picture.8  

BRDIVISORBaudrate208012001040240052048002609600130192006538400BR_CLK_I at 10MHz

BRDIVISORBaudrate1922400964800489600321440024192001628800857600411520022304001460800BR_CLK_I at 1.8432MHz

 INCORPORER Word.Picture.8  




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MiniUART IP CoreSpecification


Author: Philippe Carton
Philippe.carton2@libertysurf.fr


Rev. 0.1
 HEURE \@ "MMMM j, aaaa" September 10, 2002
This page has been intentionally left blank
Revision History

Rev.DateAuthorDescription0.128/12/01Philippe CartonFirst Draft0.25/3/02Philippe CartonDetailed Baudrate tolerance section

Contents


 RENV Introduction \h  \* FUSIONFORMAT Introduction		 RENVOIPAGE Introduction \h 1

 RENV IOports \h  \* FUSIONFORMAT IO ports 		 RENVOIPAGE IOports \h 2

 RENV Clocks \h  \* FUSIONFORMAT Clocks 		 RENVOIPAGE Clocks
 \h 3

 RENV Registers \h  \* FUSIONFORMAT Registers 		 RENVOIPAGE Registers \h 4

 RENV Operation \h  \* FUSIONFORMAT Operation 		 RENVOIPAGE Operation \h 6

 RENV Architecture \h  \* FUSIONFORMAT Architecture 		 RENVOIPAGE Architecture \h 8
1
Introduction

This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core.
It works fine connected to the serial port of a PC for data exchange with custom electronic.
It was built in the perspective to be very small, but efficient. It had to fit in a small FPGA.
It is not suited to interface a modem as there is no control handshaking (CTS/RTS).
It integrate two separate clocks, one for wishbone bus, the other for bitstream generation. This has the advantage to let the user bring his own desired frequency for the baudrate.

Support:

WISHBONE interface in 8-bit data bus
Two clock: one for wishbone interface, one for RS232 bitstream generation
Baudrate divisor from 1 to 65536 (generic parameter set at integration time)

Does not support:
FIFO input/output
Control handshaking
2
IO ports

2.1 WISHBONE interface signals

PortWidthDirectionDescriptionWB_CLK_I1InputBlocks clock inputWB_RST_I1InputAsynchronous ResetWB_ADDR_I2InputUsed for register selectionWB_DAT_I8InputData inputWB_DAT_O8OutputData outputWB_WE_I1InputWrite or read cycle selectionWB_STB_I1InputSpecifies transfer cycleWB_ACK_O1OutputAcknowledge of a transfer
2.2 Other internal signals

PortWidthDirectionDescriptionIntTx_O1OutputTransmit InterruptIntRx_O1OutputReceive InterruptBR_CLK_I1OutputClock for serialisation/unserialisation
2.3 External (off-chip) connections

PortWidthDirectionDescriptionTxD_PAD_O1OutputThe serial output signalRxD_PAD_I1InputThe serial input signal
3
Clocks
Clocks table:

NameSourceRates (MHz)RemarksDescriptionMaxMinResolutionWB_CLK_IWishbone busLimited by target hostNoneWishbone clockBR_CLK_IUserNoneBaudrate clock4
Registers

4.1 Registers list

NameAddressWidthAccessDescriptionReceive buffer08RContain byte receivedTransmit buffer08WContain byte to transmitStatus18RReceive buffer full / Transmitter busyReserved28Reserved38
4.2 Status register

Bit #AccessDescription0RTransmitter buffer state = IntTx_O pin
	0  Busy. Cant accept incoming byte
	1  Accept a byte to transmit1RReceiver buffer state = IntRx_O pin
	0  Buffer empty
	1  Buffer contain a received byte
Reset Value: XXXXXX01b

5
Operation

The UART Operation is very basic :
Upon a write to the data input bus WB_DAT_I, the core will automatically serialise and emit the byte on the TxD_PAD_O. It will hold IntTx_O low as long as it cannot accept an incoming byte. Therefore a rising edge on IntTx_O can trigger the interrupt line of a microcontroller to emit another byte.
Upon reception of a bitstream on RxD_PAD_O, the core will unserialise the information and assert IntRx_O pin. This announce that the received byte can be read on the data output bus WB_DAT_O. As soon as the byte is read, IntRx_O is negated.

Wishbone bus
The core is 8 bit wishbone compatible. It doesnt use the WB_CYC_I pin as it will never insert wait states.

Initialization
The core doesnt need to be reset, as it is ready to use upon power on.
However, a synchronous assertion of WB_RST_I will abort any pending transmit / receive and will set the core in idle state.

Baudrate divisor
A generic VHDL parameter allow the user to introduce a divisor between BR_CLK_I clock and the bitstream frequency. In addition, the core insert a 4 divisor for sampling purpose for the receiver.

Thus:
	Baudrate = Freq(BR_CLK_I) / BRDIVISOR / 4

Where BRDIVISOR is the generic parameter.

To instanciate the component in a VHDL unit, write:

U1 : MiniUART
generic map (BRDIVISOR => 103)
port map (clk, rst, adr, ...);

for a division of 103.
Below are given some divisor values for common baudrates:

Baudrate tolerance
The receiver will accept a light variation between the expected baudrate and the effective bitstream baudrate that is:

Min freqNominal Baudrate -2.60%Max freqNominal Baudrate +5.90%
Equivalent in period :
Min periodNominal period -5.90%Max periodNominal period +2.60%
Going beyond this limits, the receiver will be unable to deserialise correctly.
6
Architecture

The block diagram of the core is given:

OpenCores        MiniUART core specifications     DATE  \* FUSIONFORMAT 10/09/02

LIENHYPERTEXTE "http://www.opencores.org/"www.opencores.org     Rev 0.1 Preliminary      PAGE   of  PAGESDESECTION2

LIENHYPERTEXTE "http://www.opencores.org/"www.opencores.org   Rev 0.1  PAGE ii 

LIENHYPERTEXTE "http://www.opencores.org/"www.opencores.org     Rev 0.1  PAGE 7 of  PAGESDESECTION8


Figure  SEQ Figure \* ARABE 1 - Block Diagram of the UART core

 INCORPORER Word.Picture.8  

BRDIVISORBaudrate208012001040240052048002609600130192006538400BR_CLK_I at 10MHz

BRDIVISORBaudrate1922400964800489600321440024192001628800857600411520022304001460800BR_CLK_I at 1.8432MHz

 INCORPORER Word.Picture.8  




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