//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Wishbone Single-Port Synchronous RAM ////
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//// Wishbone Single-Port Synchronous RAM ////
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//// Memory Model ////
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//// Memory Model ////
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//// ////
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//// ////
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//// This file is part of memory library available from ////
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//// This file is part of memory library available from ////
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//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
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//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// This Wishbone controller connects to the wrapper of ////
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//// This Wishbone controller connects to the wrapper of ////
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//// the single-port synchronous memory interface. ////
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//// the single-port synchronous memory interface. ////
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//// Besides universal memory due to onchip_ram it provides a ////
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//// Besides universal memory due to onchip_ram it provides a ////
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//// generic way to set the depth of the memory. ////
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//// generic way to set the depth of the memory. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Raul Fajardo, rfajardo@gmail.com ////
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//// - Raul Fajardo, rfajardo@gmail.com ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.gnu.org/licenses/lgpl.html ////
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//// from http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// Revision History
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// Revision History
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//
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//
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//
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//
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// Revision 1.0 2009/08/18 15:15:00 fajardo
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// Revision 1.0 2009/08/18 15:15:00 fajardo
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// Created interface and tested
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// Created interface and tested
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//
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//
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`include "timescale.v"
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module minsoc_memory_model (
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module minsoc_memory_model (
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wb_clk_i, wb_rst_i,
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wb_clk_i, wb_rst_i,
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wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
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wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
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wb_stb_i, wb_ack_o, wb_err_o
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wb_stb_i, wb_ack_o, wb_err_o
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);
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);
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//
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//
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// Parameters
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// Parameters
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//
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//
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parameter adr_width = 2;
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parameter adr_width = 2;
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//
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//
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// I/O Ports
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// I/O Ports
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//
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//
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input wb_clk_i;
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input wb_clk_i;
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input wb_rst_i;
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input wb_rst_i;
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//
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//
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// WB slave i/f
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// WB slave i/f
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//
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//
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input [31:0] wb_dat_i;
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input [31:0] wb_dat_i;
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output [31:0] wb_dat_o;
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output [31:0] wb_dat_o;
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input [31:0] wb_adr_i;
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input [31:0] wb_adr_i;
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input [3:0] wb_sel_i;
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input [3:0] wb_sel_i;
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input wb_we_i;
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input wb_we_i;
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input wb_cyc_i;
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input wb_cyc_i;
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input wb_stb_i;
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input wb_stb_i;
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output wb_ack_o;
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output wb_ack_o;
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output wb_err_o;
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output wb_err_o;
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//
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//
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// Internal regs and wires
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// Internal regs and wires
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//
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//
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wire we;
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wire we;
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wire [3:0] be_i;
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wire [3:0] be_i;
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wire [31:0] wb_dat_o;
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wire [31:0] wb_dat_o;
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reg ack_we;
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reg ack_we;
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reg ack_re;
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reg ack_re;
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//
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//
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// Aliases and simple assignments
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// Aliases and simple assignments
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//
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//
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assign wb_ack_o = ack_re | ack_we;
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assign wb_ack_o = ack_re | ack_we;
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assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
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assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
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assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
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assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
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assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
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assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
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//
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//
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// Write acknowledge
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// Write acknowledge
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//
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//
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always @ (negedge wb_clk_i or posedge wb_rst_i)
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always @ (negedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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ack_we <= 1'b0;
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ack_we <= 1'b0;
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else
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else
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if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
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if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
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ack_we <= #1 1'b1;
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ack_we <= #1 1'b1;
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else
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else
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ack_we <= #1 1'b0;
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ack_we <= #1 1'b0;
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end
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end
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//
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//
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// read acknowledge
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// read acknowledge
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//
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//
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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always @ (posedge wb_clk_i or posedge wb_rst_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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ack_re <= 1'b0;
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ack_re <= 1'b0;
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else
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else
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if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
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if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
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ack_re <= #1 1'b1;
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ack_re <= #1 1'b1;
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else
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else
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ack_re <= #1 1'b0;
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ack_re <= #1 1'b0;
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end
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end
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minsoc_onchip_ram #
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minsoc_onchip_ram #
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(
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(
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.aw(adr_width)
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.aw(adr_width)
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)
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)
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block_ram_0 (
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block_ram_0 (
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.clk(wb_clk_i),
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.clk(wb_clk_i),
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.rst(wb_rst_i),
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.rst(wb_rst_i),
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.addr(wb_adr_i[adr_width+1:2]),
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.addr(wb_adr_i[adr_width+1:2]),
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.di(wb_dat_i[7:0]),
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.di(wb_dat_i[7:0]),
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.doq(wb_dat_o[7:0]),
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.doq(wb_dat_o[7:0]),
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.we(we),
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.we(we),
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.oe(1'b1),
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.oe(1'b1),
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.ce(be_i[0]));
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.ce(be_i[0]));
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minsoc_onchip_ram #
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minsoc_onchip_ram #
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(
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(
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.aw(adr_width)
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.aw(adr_width)
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)
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)
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block_ram_1 (
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block_ram_1 (
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.clk(wb_clk_i),
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.clk(wb_clk_i),
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.rst(wb_rst_i),
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.rst(wb_rst_i),
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.addr(wb_adr_i[adr_width+1:2]),
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.addr(wb_adr_i[adr_width+1:2]),
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.di(wb_dat_i[15:8]),
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.di(wb_dat_i[15:8]),
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.doq(wb_dat_o[15:8]),
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.doq(wb_dat_o[15:8]),
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.we(we),
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.we(we),
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.oe(1'b1),
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.oe(1'b1),
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.ce(be_i[1]));
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.ce(be_i[1]));
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minsoc_onchip_ram #
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minsoc_onchip_ram #
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(
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(
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.aw(adr_width)
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.aw(adr_width)
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)
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)
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block_ram_2 (
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block_ram_2 (
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.clk(wb_clk_i),
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.clk(wb_clk_i),
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.rst(wb_rst_i),
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.rst(wb_rst_i),
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.addr(wb_adr_i[adr_width+1:2]),
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.addr(wb_adr_i[adr_width+1:2]),
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.di(wb_dat_i[23:16]),
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.di(wb_dat_i[23:16]),
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.doq(wb_dat_o[23:16]),
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.doq(wb_dat_o[23:16]),
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.we(we),
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.we(we),
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.oe(1'b1),
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.oe(1'b1),
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.ce(be_i[2]));
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.ce(be_i[2]));
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minsoc_onchip_ram #
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minsoc_onchip_ram #
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(
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(
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.aw(adr_width)
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.aw(adr_width)
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)
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)
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block_ram_3 (
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block_ram_3 (
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.clk(wb_clk_i),
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.clk(wb_clk_i),
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.rst(wb_rst_i),
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.rst(wb_rst_i),
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.addr(wb_adr_i[adr_width+1:2]),
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.addr(wb_adr_i[adr_width+1:2]),
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.di(wb_dat_i[31:24]),
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.di(wb_dat_i[31:24]),
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.doq(wb_dat_o[31:24]),
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.doq(wb_dat_o[31:24]),
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.we(we),
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.we(we),
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.oe(1'b1),
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.oe(1'b1),
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.ce(be_i[3]));
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.ce(be_i[3]));
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endmodule
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endmodule
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