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`include "uart_defines.v"
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`include "uart_defines.v"
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module uart_top (
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module uart_top (
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wb_clk_i,
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wb_clk_i,
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// Wishbone signals
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// Wishbone signals
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wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
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wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
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int_o, // interrupt request
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int_o, // interrupt request
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// UART signals
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// UART signals
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// serial input/output
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// serial input/output
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stx_pad_o, srx_pad_i,
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stx_pad_o, srx_pad_i,
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// modem signals
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// modem signals
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rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
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rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
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`ifdef UART_HAS_BAUDRATE_OUTPUT
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`ifdef UART_HAS_BAUDRATE_OUTPUT
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, baud_o
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, baud_o
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`endif
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`endif
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);
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);
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parameter uart_data_width = `UART_DATA_WIDTH;
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parameter uart_data_width = `UART_DATA_WIDTH;
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parameter uart_addr_width = `UART_ADDR_WIDTH;
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parameter uart_addr_width = `UART_ADDR_WIDTH;
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input wb_clk_i;
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input wb_clk_i;
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// WISHBONE interface
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// WISHBONE interface
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input wb_rst_i;
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input wb_rst_i;
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input [uart_addr_width-1:0] wb_adr_i;
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input [uart_addr_width-1:0] wb_adr_i;
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input [uart_data_width-1:0] wb_dat_i;
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input [uart_data_width-1:0] wb_dat_i;
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output [uart_data_width-1:0] wb_dat_o;
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output [uart_data_width-1:0] wb_dat_o;
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input wb_we_i;
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input wb_we_i;
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input wb_stb_i;
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input wb_stb_i;
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input wb_cyc_i;
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input wb_cyc_i;
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input [3:0] wb_sel_i;
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input [3:0] wb_sel_i;
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output wb_ack_o;
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output wb_ack_o;
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output int_o;
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output int_o;
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// UART signals
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// UART signals
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input srx_pad_i;
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input srx_pad_i;
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output stx_pad_o;
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output stx_pad_o;
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output rts_pad_o;
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output rts_pad_o;
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input cts_pad_i;
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input cts_pad_i;
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output dtr_pad_o;
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output dtr_pad_o;
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input dsr_pad_i;
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input dsr_pad_i;
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input ri_pad_i;
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input ri_pad_i;
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input dcd_pad_i;
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input dcd_pad_i;
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// optional baudrate output
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// optional baudrate output
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`ifdef UART_HAS_BAUDRATE_OUTPUT
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`ifdef UART_HAS_BAUDRATE_OUTPUT
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output baud_o;
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output baud_o;
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`endif
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`endif
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endmodule
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endmodule
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