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| Rev 85 |
Rev 109 |
PROJECT_DIR=rtl/verilog/uart16550/rtl/verilog
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PROJECT_DIR=rtl/verilog/uart16550/rtl/verilog
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PROJECT_SRC=(uart_top.v
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PROJECT_SRC=(uart_top.v
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uart_sync_flops.v
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uart_sync_flops.v
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uart_transmitter.v
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uart_transmitter.v
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uart_debug_if.v
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uart_debug_if.v
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uart_wb.v
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uart_wb.v
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uart_receiver.v
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uart_receiver.v
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uart_tfifo.v
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uart_tfifo.v
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uart_regs.v
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uart_regs.v
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uart_rfifo.v
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uart_rfifo.v
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uart_defines.v
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uart_defines.v
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raminfr.v)
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raminfr.v)
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