`include "minsoc_bench_defines.v"
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`include "minsoc_bench_defines.v"
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`include "minsoc_defines.v"
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`include "minsoc_defines.v"
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`include "timescale.v"
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`include "timescale.v"
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module minsoc_bench_clock();
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module minsoc_bench_clock();
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`ifdef POSITIVE_RESET
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`ifdef POSITIVE_RESET
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localparam RESET_LEVEL = 1'b1;
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localparam RESET_LEVEL = 1'b1;
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`elsif NEGATIVE_RESET
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`elsif NEGATIVE_RESET
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localparam RESET_LEVEL = 1'b0;
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localparam RESET_LEVEL = 1'b0;
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`else
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`else
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localparam RESET_LEVEL = 1'b1;
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localparam RESET_LEVEL = 1'b1;
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`endif
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`endif
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reg clock, reset, eth_tx_clk, eth_rx_clk;
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reg clock, reset, eth_tx_clk, eth_rx_clk;
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minsoc_bench_core minsoc_bench_core_0(
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minsoc_bench_core minsoc_bench_core_0(
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.clock(clock),
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.clock(clock),
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.reset(reset),
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.reset(reset),
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.eth_tx_clk(eth_tx_clk),
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.eth_tx_clk(eth_tx_clk),
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.eth_rx_clk(eth_rx_clk)
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.eth_rx_clk(eth_rx_clk)
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);
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);
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initial begin
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initial begin
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reset = ~RESET_LEVEL;
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reset = ~RESET_LEVEL;
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clock = 1'b0;
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clock = 1'b0;
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eth_tx_clk = 1'b0;
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eth_tx_clk = 1'b0;
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eth_rx_clk = 1'b0;
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eth_rx_clk = 1'b0;
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// Reset controller
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// Reset controller
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repeat (2) @ (negedge clock);
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repeat (2) @ (negedge clock);
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reset = RESET_LEVEL;
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reset = RESET_LEVEL;
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repeat (16) @ (negedge clock);
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repeat (16) @ (negedge clock);
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reset = ~RESET_LEVEL;
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reset = ~RESET_LEVEL;
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end
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end
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//
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//
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// Regular clocking and output
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// Regular clocking and output
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//
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//
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always begin
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always begin
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#((`CLK_PERIOD)/2) clock <= ~clock;
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#((`CLK_PERIOD)/2) clock <= ~clock;
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end
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end
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//Generate tx and rx clocks
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//Generate tx and rx clocks
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always begin
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always begin
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#((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk;
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#((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk;
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end
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end
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always begin
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always begin
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#((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk;
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#((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk;
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end
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end
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//~Generate tx and rx clocks
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//~Generate tx and rx clocks
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endmodule
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endmodule
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