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//
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// Define FPGA manufacturer
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//
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`define GENERIC_FPGA
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//`define ALTERA_FPGA
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//`define XILINX_FPGA
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//
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// Define Xilinx FPGA family
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//
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`ifdef XILINX_FPGA
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//`define SPARTAN2
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//`define SPARTAN3
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//`define SPARTAN3E
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`define SPARTAN3A
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//`define VIRTEX
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//`define VIRTEX2
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//`define VIRTEX4
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//`define VIRTEX5
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//
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// Define Altera FPGA family
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//
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`elsif ALTERA_FPGA
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//`define ARRIA_GX
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//`define ARRIA_II_GX
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//`define CYCLONE_I
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//`define CYCLONE_II
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`define CYCLONE_III
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//`define CYCLONE_III_LS
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//`define CYCLONE_IV_E
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//`define CYCLONE_IV_GS
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|
//`define MAX_II
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|
//`define MAX_V
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|
//`define MAX3000A
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|
//`define MAX7000AE
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|
//`define MAX7000B
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|
//`define MAX7000S
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|
//`define STRATIX
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|
//`define STRATIX_II
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|
//`define STRATIX_II_GX
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|
//`define STRATIX_III
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`endif
|
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|
|
//
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|
// Memory
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|
//
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|
`define MEMORY_ADR_WIDTH 13 //MEMORY_ADR_WIDTH IS NOT ALLOWED TO BE LESS THAN 12,
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//memory is composed by blocks of address width 11
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|
//Address width of memory -> select memory depth,
|
|
//2 powers MEMORY_ADR_WIDTH defines the memory depth
|
|
//the memory data width is 32 bit,
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//memory amount in Bytes = 4*memory depth
|
|
|
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//
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|
// Memory type (uncomment something if ASIC or generic memory)
|
|
//
|
|
//`define GENERIC_MEMORY
|
|
//`define AVANT_ATP
|
|
//`define VIRAGE_SSP
|
|
//`define VIRTUALSILICON_SSP
|
|
|
|
|
|
//
|
|
// TAP selection
|
|
//
|
|
//`define GENERIC_TAP
|
|
`define FPGA_TAP
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|
|
|
//
|
|
// Clock Division selection
|
|
//
|
|
//`define NO_CLOCK_DIVISION
|
|
//`define GENERIC_CLOCK_DIVISION
|
|
`define FPGA_CLOCK_DIVISION // For Altera ALTPLL, only CYCLONE_III family has been tested.
|
|
|
|
//
|
|
// Define division
|
|
//
|
|
`define CLOCK_DIVISOR 5 //in case of GENERIC_CLOCK_DIVISION the real value will be rounded
|
|
//down to an even value in FPGA case, check minsoc_clock_manager
|
|
//for allowed divisors.
|
|
//DO NOT USE CLOCK_DIVISOR = 1 COMMENT THE CLOCK DIVISION SELECTION
|
|
//INSTEAD.
|
|
|
|
//
|
|
// Reset polarity
|
|
//
|
|
`define NEGATIVE_RESET //rstn
|
|
//`define POSITIVE_RESET //rst
|
|
|
|
//
|
|
// Start-up circuit (only necessary later to load firmware automatically from SPI memory)
|
|
//
|
|
//`define START_UP
|
|
|
|
//
|
|
// Connected modules
|
|
//
|
|
`define UART
|
|
`define ETHERNET
|
|
|
|
//
|
|
// Ethernet reset
|
|
//
|
|
`define ETH_RESET 1'b0
|
|
//`define ETH_RESET 1'b1
|
|
|
|
//
|
|
// Interrupts
|
|
//
|
|
`define APP_INT_RES1 1:0
|
|
`define APP_INT_UART 2
|
|
`define APP_INT_RES2 3
|
|
`define APP_INT_ETH 4
|
|
`define APP_INT_PS2 5
|
|
`define APP_INT_RES3 19:6
|
|
|
|
//
|
|
// Address map
|
|
//
|
|
`define APP_ADDR_DEC_W 8
|
|
`define APP_ADDR_SRAM `APP_ADDR_DEC_W'h00
|
|
`define APP_ADDR_FLASH `APP_ADDR_DEC_W'h04
|
|
`define APP_ADDR_DECP_W 4
|
|
`define APP_ADDR_PERIP `APP_ADDR_DECP_W'h9
|
|
`define APP_ADDR_SPI `APP_ADDR_DEC_W'h97
|
|
`define APP_ADDR_ETH `APP_ADDR_DEC_W'h92
|
|
`define APP_ADDR_AUDIO `APP_ADDR_DEC_W'h9d
|
|
`define APP_ADDR_UART `APP_ADDR_DEC_W'h90
|
|
`define APP_ADDR_PS2 `APP_ADDR_DEC_W'h94
|
|
`define APP_ADDR_RES1 `APP_ADDR_DEC_W'h9e
|
|
`define APP_ADDR_RES2 `APP_ADDR_DEC_W'h9f
|
|
|
|
//
|
|
// Set-up GENERIC_TAP, GENERIC_MEMORY if GENERIC_FPGA was chosen
|
|
// and GENERIC_CLOCK_DIVISION if NO_CLOCK_DIVISION was not set
|
|
//
|
|
`ifdef GENERIC_FPGA
|
|
`undef FPGA_TAP
|
|
`undef FPGA_CLOCK_DIVISION
|
|
|
|
`define GENERIC_TAP
|
|
`define GENERIC_MEMORY
|
|
`ifndef NO_CLOCK_DIVISION
|
|
`define GENERIC_CLOCK_DIVISION
|
|
`endif
|
|
`endif
|
|
|
No newline at end of file
|
No newline at end of file
|
