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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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/*
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/*
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* File : Add.v
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* File : Add.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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*
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* Modification History:
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* Modification History:
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* Rev Date Initials Description of Change
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* Rev Date Initials Description of Change
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* 1.0 7-Jun-2011 GEA Initial design.
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* 1.0 7-Jun-2011 GEA Initial design.
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*
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*
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* Standards/Formatting:
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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* Verilog 2001, 4 soft tab, wide column.
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*
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*
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* Description:
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* Description:
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* A simple 32-bit 2-input adder.
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* A simple 32-bit 2-input adder.
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*/
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*/
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module Add(
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module Add(
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input [31:0] A,
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input [31:0] A,
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input [31:0] B,
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input [31:0] B,
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output [31:0] C
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output [31:0] C
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);
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);
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assign C = (A + B);
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assign C = (A + B);
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endmodule
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endmodule
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