`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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/*
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/*
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* File : MemControl.v
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* File : MemControl.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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*
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* Modification History:
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* Modification History:
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* Rev Date Initials Description of Change
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* Rev Date Initials Description of Change
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* 1.0 24-Jun-2011 GEA Initial design.
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* 1.0 24-Jun-2011 GEA Initial design.
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* 2.0 28-Jun-2012 GEA Expanded from a simple byte/half/word unit to
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* 2.0 28-Jun-2012 GEA Expanded from a simple byte/half/word unit to
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* An advanced data memory controller capable of
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* An advanced data memory controller capable of
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* handling big/little endian, atomic and unaligned
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* handling big/little endian, atomic and unaligned
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* memory accesses.
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* memory accesses.
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*
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*
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* Standards/Formatting:
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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* Verilog 2001, 4 soft tab, wide column.
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*
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*
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* Description:
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* Description:
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* A Data Memory Controller which handles all read and write requests from the
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* A Data Memory Controller which handles all read and write requests from the
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* processor to data memory. All data accesses--whether big endian, little endian,
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* processor to data memory. All data accesses--whether big endian, little endian,
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* byte, half, word, or unaligned transfers--are transformed into a simple read
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* byte, half, word, or unaligned transfers--are transformed into a simple read
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* and write command to data memory over a 32-bit data bus, where the read command
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* and write command to data memory over a 32-bit data bus, where the read command
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* is one bit and the write command is 4 bits, one for each byte in the 32-bit word.
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* is one bit and the write command is 4 bits, one for each byte in the 32-bit word.
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*/
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*/
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module MemControl(
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module MemControl(
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input clock,
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input clock,
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input reset,
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input reset,
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input [31:0] DataIn, // Data from CPU
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input [31:0] DataIn, // Data from CPU
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input [31:0] Address, // From CPU
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input [31:0] Address, // From CPU
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input [31:0] MReadData, // Data from Memory
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input [31:0] MReadData, // Data from Memory
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input MemRead, // Memory Read command from CPU
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input MemRead, // Memory Read command from CPU
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input MemWrite, // Memory Write command from CPU
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input MemWrite, // Memory Write command from CPU
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input DataMem_Ready, // Ready signal from Memory
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input DataMem_Ready, // Ready signal from Memory
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input Byte, // Load/Store is Byte (8-bit)
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input Byte, // Load/Store is Byte (8-bit)
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input Half, // Load/Store is Half (16-bit)
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input Half, // Load/Store is Half (16-bit)
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input SignExtend, // Sub-word load should be sign extended
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input SignExtend, // Sub-word load should be sign extended
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input KernelMode, // (Exception logic)
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input KernelMode, // (Exception logic)
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input ReverseEndian, // Reverse Endian Memory for User Mode
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input ReverseEndian, // Reverse Endian Memory for User Mode
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input LLSC, // (LLSC logic)
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input LLSC, // (LLSC logic)
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input ERET, // (LLSC logic)
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input ERET, // (LLSC logic)
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input Left, // Unaligned Load/Store Word Left
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input Left, // Unaligned Load/Store Word Left
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input Right, // Unaligned Load/Store Word Right
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input Right, // Unaligned Load/Store Word Right
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input M_Exception_Stall,
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input M_Exception_Stall,
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input IF_Stall, // XXX Clean this up between this module and HAZ/FWD
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input IF_Stall, // XXX Clean this up between this module and HAZ/FWD
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output reg [31:0] DataOut, // Data to CPU
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output reg [31:0] DataOut, // Data to CPU
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output [31:0] MWriteData, // Data to Memory
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output [31:0] MWriteData, // Data to Memory
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output reg [3:0] WriteEnable, // Write Enable to Memory for each of 4 bytes of Memory
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output reg [3:0] WriteEnable, // Write Enable to Memory for each of 4 bytes of Memory
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output ReadEnable, // Read Enable to Memory
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output ReadEnable, // Read Enable to Memory
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output M_Stall,
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output M_Stall,
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output EXC_AdEL, // Load Exception
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output EXC_AdEL, // Load Exception
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output EXC_AdES // Store Exception
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output EXC_AdES // Store Exception
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);
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);
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`include "MIPS_Parameters.v"
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`include "MIPS_Parameters.v"
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|
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/*** Reverse Endian Mode
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/*** Reverse Endian Mode
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Normal memory accesses in the processor are Big Endian. The endianness can be reversed
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Normal memory accesses in the processor are Big Endian. The endianness can be reversed
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to Little Endian in User Mode only.
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to Little Endian in User Mode only.
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*/
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*/
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wire BE = KernelMode | ~ReverseEndian;
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wire BE = KernelMode | ~ReverseEndian;
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|
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/*** Indicator that the current memory reference must be word-aligned ***/
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/*** Indicator that the current memory reference must be word-aligned ***/
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wire Word = ~(Half | Byte | Left | Right);
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wire Word = ~(Half | Byte | Left | Right);
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|
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// Exception Detection
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// Exception Detection
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wire EXC_KernelMem = ~KernelMode & (Address < UMem_Lower);
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wire EXC_KernelMem = ~KernelMode & (Address < UMem_Lower);
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wire EXC_Word = Word & (Address[1] | Address[0]);
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wire EXC_Word = Word & (Address[1] | Address[0]);
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wire EXC_Half = Half & Address[0];
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wire EXC_Half = Half & Address[0];
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assign EXC_AdEL = MemRead & (EXC_KernelMem | EXC_Word | EXC_Half);
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assign EXC_AdEL = MemRead & (EXC_KernelMem | EXC_Word | EXC_Half);
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assign EXC_AdES = MemWrite & (EXC_KernelMem | EXC_Word | EXC_Half);
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assign EXC_AdES = MemWrite & (EXC_KernelMem | EXC_Word | EXC_Half);
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|
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/*** Load Linked and Store Conditional logic ***
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/*** Load Linked and Store Conditional logic ***
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|
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A 32-bit register keeps track of the address for atomic Load Linked / Store Conditional
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A 32-bit register keeps track of the address for atomic Load Linked / Store Conditional
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operations. This register can be updated during stalls since it is not visible to
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operations. This register can be updated during stalls since it is not visible to
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forward stages. It does not need to be flushed during exceptions, since ERET destroys
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forward stages. It does not need to be flushed during exceptions, since ERET destroys
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the atomicity condition and there are no detrimental effects in an exception handler.
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the atomicity condition and there are no detrimental effects in an exception handler.
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|
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The atomic condition is set with a Load Linked instruction, and cleared on an ERET
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The atomic condition is set with a Load Linked instruction, and cleared on an ERET
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instruction or when any store instruction writes to one or more bytes covered by
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instruction or when any store instruction writes to one or more bytes covered by
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the word address register. It does not update on a stall condition.
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the word address register. It does not update on a stall condition.
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The MIPS32 spec states that an ERET instruction between LL and SC will cause the
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The MIPS32 spec states that an ERET instruction between LL and SC will cause the
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atomicity condition to fail. This implementation uses the ERET signal from the ID
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atomicity condition to fail. This implementation uses the ERET signal from the ID
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stage, which means instruction sequences such as "LL SC" could appear to have an
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stage, which means instruction sequences such as "LL SC" could appear to have an
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ERET instruction between them even though they don't. One way to fix this is to pass
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ERET instruction between them even though they don't. One way to fix this is to pass
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the ERET signal through the pipeline to the MEM stage. However, because of the nature
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the ERET signal through the pipeline to the MEM stage. However, because of the nature
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of LL/SC operations (they occur in a loop which checks the result at each iteration),
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of LL/SC operations (they occur in a loop which checks the result at each iteration),
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an ERET will normally never be inserted into the pipeline programmatically until the
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an ERET will normally never be inserted into the pipeline programmatically until the
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LL/SC sequence has completed (exceptions such as interrupts can still cause ERET, but
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LL/SC sequence has completed (exceptions such as interrupts can still cause ERET, but
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they can still cause them in the LL SC sequence as well). In other words, by not passing
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they can still cause them in the LL SC sequence as well). In other words, by not passing
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ERET through the pipeline, the only possible effect is a performance penalty. Also this
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ERET through the pipeline, the only possible effect is a performance penalty. Also this
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may be irrelevant since currently ERET stalls for forward stages which can cause exceptions,
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may be irrelevant since currently ERET stalls for forward stages which can cause exceptions,
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which includes LL and SC.
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which includes LL and SC.
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*/
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*/
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reg [29:0] LLSC_Address;
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reg [29:0] LLSC_Address;
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reg LLSC_Atomic;
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reg LLSC_Atomic;
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wire LLSC_MemWrite_Mask;
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wire LLSC_MemWrite_Mask;
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|
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always @(posedge clock) begin
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always @(posedge clock) begin
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LLSC_Address <= (reset) ? 30'b0 : (MemRead & LLSC) ? Address[31:2] : LLSC_Address;
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LLSC_Address <= (reset) ? 30'b0 : (MemRead & LLSC) ? Address[31:2] : LLSC_Address;
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end
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end
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always @(posedge clock) begin
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always @(posedge clock) begin
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if (reset) begin
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if (reset) begin
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LLSC_Atomic <= 0;
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LLSC_Atomic <= 0;
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end
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end
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else if (MemRead) begin
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else if (MemRead) begin
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LLSC_Atomic <= (LLSC) ? 1 : LLSC_Atomic;
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LLSC_Atomic <= (LLSC) ? 1 : LLSC_Atomic;
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end
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end
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// XXX GEA Bug for Ganesh: remove "& ~IF_Stall" from below, then SC will always fail:
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// XXX GEA Bug for Ganesh: remove "& ~IF_Stall" from below, then SC will always fail:
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else if (ERET | (~M_Stall & ~IF_Stall & MemWrite & (Address[31:2] == LLSC_Address))) begin
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else if (ERET | (~M_Stall & ~IF_Stall & MemWrite & (Address[31:2] == LLSC_Address))) begin
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LLSC_Atomic <= 0;
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LLSC_Atomic <= 0;
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end
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end
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else begin
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else begin
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LLSC_Atomic <= LLSC_Atomic;
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LLSC_Atomic <= LLSC_Atomic;
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end
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end
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end
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end
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assign LLSC_MemWrite_Mask = (LLSC & MemWrite & (~LLSC_Atomic | (Address[31:2] != LLSC_Address)));
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assign LLSC_MemWrite_Mask = (LLSC & MemWrite & (~LLSC_Atomic | (Address[31:2] != LLSC_Address)));
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|
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wire WriteCondition = MemWrite & ~(EXC_KernelMem | EXC_Word | EXC_Half) & ~LLSC_MemWrite_Mask;
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wire WriteCondition = MemWrite & ~(EXC_KernelMem | EXC_Word | EXC_Half) & ~LLSC_MemWrite_Mask;
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wire ReadCondition = MemRead & ~(EXC_KernelMem | EXC_Word | EXC_Half);
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wire ReadCondition = MemRead & ~(EXC_KernelMem | EXC_Word | EXC_Half);
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|
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reg RW_Mask;
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reg RW_Mask;
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always @(posedge clock) begin
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always @(posedge clock) begin
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RW_Mask <= (reset) ? 0 : (((MemWrite | MemRead) & DataMem_Ready) ? 1 : ((~M_Stall & ~IF_Stall) ? 0 : RW_Mask));
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RW_Mask <= (reset) ? 0 : (((MemWrite | MemRead) & DataMem_Ready) ? 1 : ((~M_Stall & ~IF_Stall) ? 0 : RW_Mask));
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end
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end
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assign M_Stall = ReadEnable | (WriteEnable != 4'b0000) | DataMem_Ready | M_Exception_Stall;
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assign M_Stall = ReadEnable | (WriteEnable != 4'b0000) | DataMem_Ready | M_Exception_Stall;
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assign ReadEnable = ReadCondition & ~RW_Mask;
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assign ReadEnable = ReadCondition & ~RW_Mask;
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|
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wire Half_Access_L = (Address[1] ^ BE);
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wire Half_Access_L = (Address[1] ^ BE);
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wire Half_Access_R = (Address[1] ~^ BE);
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wire Half_Access_R = (Address[1] ~^ BE);
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wire Byte_Access_LL = Half_Access_L & (Address[1] ~^ Address[0]);
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wire Byte_Access_LL = Half_Access_L & (Address[1] ~^ Address[0]);
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wire Byte_Access_LM = Half_Access_L & (Address[0] ~^ BE);
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wire Byte_Access_LM = Half_Access_L & (Address[0] ~^ BE);
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wire Byte_Access_RM = Half_Access_R & (Address[0] ^ BE);
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wire Byte_Access_RM = Half_Access_R & (Address[0] ^ BE);
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wire Byte_Access_RR = Half_Access_R & (Address[1] ~^ Address[0]);
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wire Byte_Access_RR = Half_Access_R & (Address[1] ~^ Address[0]);
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|
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// Write-Enable Signals to Memory
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// Write-Enable Signals to Memory
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always @(*) begin
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always @(*) begin
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if (WriteCondition & ~RW_Mask) begin
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if (WriteCondition & ~RW_Mask) begin
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if (Byte) begin
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if (Byte) begin
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WriteEnable[3] <= Byte_Access_LL;
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WriteEnable[3] <= Byte_Access_LL;
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WriteEnable[2] <= Byte_Access_LM;
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WriteEnable[2] <= Byte_Access_LM;
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WriteEnable[1] <= Byte_Access_RM;
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WriteEnable[1] <= Byte_Access_RM;
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WriteEnable[0] <= Byte_Access_RR;
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WriteEnable[0] <= Byte_Access_RR;
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end
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end
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else if (Half) begin
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else if (Half) begin
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WriteEnable[3] <= Half_Access_L;
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WriteEnable[3] <= Half_Access_L;
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WriteEnable[2] <= Half_Access_L;
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WriteEnable[2] <= Half_Access_L;
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WriteEnable[1] <= Half_Access_R;
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WriteEnable[1] <= Half_Access_R;
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WriteEnable[0] <= Half_Access_R;
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WriteEnable[0] <= Half_Access_R;
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end
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end
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else if (Left) begin
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else if (Left) begin
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case (Address[1:0])
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case (Address[1:0])
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2'b00 : WriteEnable <= (BE) ? 4'b1111 : 4'b0001;
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2'b00 : WriteEnable <= (BE) ? 4'b1111 : 4'b0001;
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2'b01 : WriteEnable <= (BE) ? 4'b0111 : 4'b0011;
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2'b01 : WriteEnable <= (BE) ? 4'b0111 : 4'b0011;
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2'b10 : WriteEnable <= (BE) ? 4'b0011 : 4'b0111;
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2'b10 : WriteEnable <= (BE) ? 4'b0011 : 4'b0111;
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2'b11 : WriteEnable <= (BE) ? 4'b0001 : 4'b1111;
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2'b11 : WriteEnable <= (BE) ? 4'b0001 : 4'b1111;
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endcase
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endcase
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end
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end
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else if (Right) begin
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else if (Right) begin
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case (Address[1:0])
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case (Address[1:0])
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2'b00 : WriteEnable <= (BE) ? 4'b1000 : 4'b1111;
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2'b00 : WriteEnable <= (BE) ? 4'b1000 : 4'b1111;
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2'b01 : WriteEnable <= (BE) ? 4'b1100 : 4'b1110;
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2'b01 : WriteEnable <= (BE) ? 4'b1100 : 4'b1110;
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2'b10 : WriteEnable <= (BE) ? 4'b1110 : 4'b1100;
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2'b10 : WriteEnable <= (BE) ? 4'b1110 : 4'b1100;
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2'b11 : WriteEnable <= (BE) ? 4'b1111 : 4'b1000;
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2'b11 : WriteEnable <= (BE) ? 4'b1111 : 4'b1000;
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endcase
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endcase
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end
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end
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else begin
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else begin
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WriteEnable <= 4'b1111;
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WriteEnable <= 4'b1111;
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end
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end
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end
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end
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else begin
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else begin
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WriteEnable <= 4'b0000;
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WriteEnable <= 4'b0000;
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end
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end
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end
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end
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|
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// Data Going to Memory
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// Data Going to Memory
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assign MWriteData[31:24] = (Byte) ? DataIn[7:0] : ((Half) ? DataIn[15:8] : DataIn[31:24]);
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assign MWriteData[31:24] = (Byte) ? DataIn[7:0] : ((Half) ? DataIn[15:8] : DataIn[31:24]);
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assign MWriteData[23:16] = (Byte | Half) ? DataIn[7:0] : DataIn[23:16];
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assign MWriteData[23:16] = (Byte | Half) ? DataIn[7:0] : DataIn[23:16];
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assign MWriteData[15:8] = (Byte) ? DataIn[7:0] : DataIn[15:8];
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assign MWriteData[15:8] = (Byte) ? DataIn[7:0] : DataIn[15:8];
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assign MWriteData[7:0] = DataIn[7:0];
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assign MWriteData[7:0] = DataIn[7:0];
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|
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// Data Read from Memory
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// Data Read from Memory
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always @(*) begin
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always @(*) begin
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if (Byte) begin
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if (Byte) begin
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if (Byte_Access_LL) begin
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if (Byte_Access_LL) begin
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DataOut <= (SignExtend & MReadData[31]) ? {24'hFFFFFF, MReadData[31:24]} : {24'h000000, MReadData[31:24]};
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DataOut <= (SignExtend & MReadData[31]) ? {24'hFFFFFF, MReadData[31:24]} : {24'h000000, MReadData[31:24]};
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end
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end
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else if (Byte_Access_LM) begin
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else if (Byte_Access_LM) begin
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DataOut <= (SignExtend & MReadData[23]) ? {24'hFFFFFF, MReadData[23:16]} : {24'h000000, MReadData[23:16]};
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DataOut <= (SignExtend & MReadData[23]) ? {24'hFFFFFF, MReadData[23:16]} : {24'h000000, MReadData[23:16]};
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end
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end
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else if (Byte_Access_RM) begin
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else if (Byte_Access_RM) begin
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DataOut <= (SignExtend & MReadData[15]) ? {24'hFFFFFF, MReadData[15:8]} : {24'h000000, MReadData[15:8]};
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DataOut <= (SignExtend & MReadData[15]) ? {24'hFFFFFF, MReadData[15:8]} : {24'h000000, MReadData[15:8]};
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end
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end
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else begin
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else begin
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DataOut <= (SignExtend & MReadData[7]) ? {24'hFFFFFF, MReadData[7:0]} : {24'h000000, MReadData[7:0]};
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DataOut <= (SignExtend & MReadData[7]) ? {24'hFFFFFF, MReadData[7:0]} : {24'h000000, MReadData[7:0]};
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end
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end
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end
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end
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else if (Half) begin
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else if (Half) begin
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if (Half_Access_L) begin
|
if (Half_Access_L) begin
|
DataOut <= (SignExtend & MReadData[31]) ? {16'hFFFF, MReadData[31:16]} : {16'h0000, MReadData[31:16]};
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DataOut <= (SignExtend & MReadData[31]) ? {16'hFFFF, MReadData[31:16]} : {16'h0000, MReadData[31:16]};
|
end
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end
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else begin
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else begin
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DataOut <= (SignExtend & MReadData[15]) ? {16'hFFFF, MReadData[15:0]} : {16'h0000, MReadData[15:0]};
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DataOut <= (SignExtend & MReadData[15]) ? {16'hFFFF, MReadData[15:0]} : {16'h0000, MReadData[15:0]};
|
end
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end
|
end
|
end
|
else if (LLSC & MemWrite) begin
|
else if (LLSC & MemWrite) begin
|
DataOut <= (LLSC_Atomic & (Address[31:2] == LLSC_Address)) ? 32'h0000_0001 : 32'h0000_0000;
|
DataOut <= (LLSC_Atomic & (Address[31:2] == LLSC_Address)) ? 32'h0000_0001 : 32'h0000_0000;
|
end
|
end
|
else if (Left) begin
|
else if (Left) begin
|
case (Address[1:0])
|
case (Address[1:0])
|
2'b00 : DataOut <= (BE) ? MReadData : {MReadData[7:0], DataIn[23:0]};
|
2'b00 : DataOut <= (BE) ? MReadData : {MReadData[7:0], DataIn[23:0]};
|
2'b01 : DataOut <= (BE) ? {MReadData[23:0], DataIn[7:0]} : {MReadData[15:0], DataIn[15:0]};
|
2'b01 : DataOut <= (BE) ? {MReadData[23:0], DataIn[7:0]} : {MReadData[15:0], DataIn[15:0]};
|
2'b10 : DataOut <= (BE) ? {MReadData[15:0], DataIn[15:0]} : {MReadData[23:0], DataIn[7:0]};
|
2'b10 : DataOut <= (BE) ? {MReadData[15:0], DataIn[15:0]} : {MReadData[23:0], DataIn[7:0]};
|
2'b11 : DataOut <= (BE) ? {MReadData[7:0], DataIn[23:0]} : MReadData;
|
2'b11 : DataOut <= (BE) ? {MReadData[7:0], DataIn[23:0]} : MReadData;
|
endcase
|
endcase
|
end
|
end
|
else if (Right) begin
|
else if (Right) begin
|
case (Address[1:0])
|
case (Address[1:0])
|
2'b00 : DataOut <= (BE) ? {DataIn[31:8], MReadData[31:24]} : MReadData;
|
2'b00 : DataOut <= (BE) ? {DataIn[31:8], MReadData[31:24]} : MReadData;
|
2'b01 : DataOut <= (BE) ? {DataIn[31:16], MReadData[31:16]} : {DataIn[31:24], MReadData[31:8]};
|
2'b01 : DataOut <= (BE) ? {DataIn[31:16], MReadData[31:16]} : {DataIn[31:24], MReadData[31:8]};
|
2'b10 : DataOut <= (BE) ? {DataIn[31:24], MReadData[31:8]} : {DataIn[31:16], MReadData[31:16]};
|
2'b10 : DataOut <= (BE) ? {DataIn[31:24], MReadData[31:8]} : {DataIn[31:16], MReadData[31:16]};
|
2'b11 : DataOut <= (BE) ? MReadData : {DataIn[31:8], MReadData[31:24]};
|
2'b11 : DataOut <= (BE) ? MReadData : {DataIn[31:8], MReadData[31:24]};
|
endcase
|
endcase
|
end
|
end
|
else begin
|
else begin
|
DataOut <= MReadData;
|
DataOut <= MReadData;
|
end
|
end
|
end
|
end
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|
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endmodule
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endmodule
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