`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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/*
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/*
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* File : BRAM_592KB_Wrapper.v
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* File : BRAM_592KB_Wrapper.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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*
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* Modification History:
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* Modification History:
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* Rev Date Initials Description of Change
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* Rev Date Initials Description of Change
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* 1.0 6-Jun-2012 GEA Initial design.
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* 1.0 6-Jun-2012 GEA Initial design.
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*
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*
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* Standards/Formatting:
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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* Verilog 2001, 4 soft tab, wide column.
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*
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*
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* Description:
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* Description:
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* Provides access to Block Memory through a 4-way handshaking protocol,
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* Provides access to Block Memory through a 4-way handshaking protocol,
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* which allows for multi-cycle and variably-timed operations on the
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* which allows for multi-cycle and variably-timed operations on the
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* data bus.
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* data bus.
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*/
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*/
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module BRAM_592KB_Wrapper(
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module BRAM_592KB_Wrapper(
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input clock,
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input clock,
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input reset,
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input reset,
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input rea,
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input rea,
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input [3:0] wea,
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input [3:0] wea,
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input [17:0] addra,
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input [17:0] addra,
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input [31:0] dina,
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input [31:0] dina,
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output [31:0] douta,
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output [31:0] douta,
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output reg dreadya,
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output reg dreadya,
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input reb,
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input reb,
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input [3:0] web,
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input [3:0] web,
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input [17:0] addrb,
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input [17:0] addrb,
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input [31:0] dinb,
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input [31:0] dinb,
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output [31:0] doutb,
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output [31:0] doutb,
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output reg dreadyb
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output reg dreadyb
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);
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);
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/* Four-Way Memory Handshake Protocol:
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/* Four-Way Memory Handshake Protocol:
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1. Read/Write request goes high.
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1. Read/Write request goes high.
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2. Ack goes high when data is available.
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2. Ack goes high when data is available.
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3. Read/Write request goes low.
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3. Read/Write request goes low.
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4. Ack signal goes low.
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4. Ack signal goes low.
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____
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____
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R/W: __| |____
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R/W: __| |____
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____
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____
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Ack: _____| |____
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Ack: _____| |____
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*/
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*/
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// Writes require one clock cycle, and reads require 2 or 3 clock cycles (registered output).
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// Writes require one clock cycle, and reads require 2 or 3 clock cycles (registered output).
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// The following logic controls the Ready signal based on these latencies.
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// The following logic controls the Ready signal based on these latencies.
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reg [1:0] delay_A, delay_B;
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reg [1:0] delay_A, delay_B;
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always @(posedge clock) begin
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always @(posedge clock) begin
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delay_A <= (reset | ~rea) ? 2'b00 : ((delay_A == 2'b10) ? delay_A : delay_A + 1);
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delay_A <= (reset | ~rea) ? 2'b00 : ((delay_A == 2'b10) ? delay_A : delay_A + 1);
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delay_B <= (reset | ~reb) ? 2'b00 : ((delay_B == 2'b10) ? delay_B : delay_B + 1);
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delay_B <= (reset | ~reb) ? 2'b00 : ((delay_B == 2'b10) ? delay_B : delay_B + 1);
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end
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end
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always @(posedge clock) begin
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always @(posedge clock) begin
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dreadya <= (reset) ? 0 : ((wea != 4'b0000) || ((delay_A == 2'b10) && rea)) ? 1 : 0;
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dreadya <= (reset) ? 0 : ((wea != 4'b0000) || ((delay_A == 2'b10) && rea)) ? 1 : 0;
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dreadyb <= (reset) ? 0 : ((web != 4'b0000) || ((delay_B == 2'b10) && reb)) ? 1 : 0;
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dreadyb <= (reset) ? 0 : ((web != 4'b0000) || ((delay_B == 2'b10) && reb)) ? 1 : 0;
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end
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end
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BRAM_592KB_2R RAM (
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BRAM_592KB_2R RAM (
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.clka (clock), // input clka
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.clka (clock), // input clka
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.rsta (reset), // input rsta
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.rsta (reset), // input rsta
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.wea (wea), // input [3 : 0] wea
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.wea (wea), // input [3 : 0] wea
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.addra (addra), // input [17 : 0] addra
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.addra (addra), // input [17 : 0] addra
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.dina (dina), // input [31 : 0] dina
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.dina (dina), // input [31 : 0] dina
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.douta (douta), // output [31 : 0] douta
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.douta (douta), // output [31 : 0] douta
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.clkb (clock), // input clkb
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.clkb (clock), // input clkb
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.rstb (reset), // input rstb
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.rstb (reset), // input rstb
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.web (web), // input [3 : 0] web
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.web (web), // input [3 : 0] web
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.addrb (addrb), // input [17 : 0] addrb
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.addrb (addrb), // input [17 : 0] addrb
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.dinb (dinb), // input [31 : 0] dinb
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.dinb (dinb), // input [31 : 0] dinb
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.doutb (doutb) // output [31 : 0] doutb
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.doutb (doutb) // output [31 : 0] doutb
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);
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);
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endmodule
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endmodule
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