`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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/*
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/*
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* File : I2C_Clock.v
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* File : I2C_Clock.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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*
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* Modification History:
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* Modification History:
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* Rev Date Initials Description of Change
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* Rev Date Initials Description of Change
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* 1.0 21-Jun-2012 GEA Initial design.
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* 1.0 21-Jun-2012 GEA Initial design.
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*
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*
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* Standards/Formatting:
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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* Verilog 2001, 4 soft tab, wide column.
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*
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*
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* Description:
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* Description:
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* Generates a 100 kHz clock signal and an indicator which pulses
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* Generates a 100 kHz clock signal and an indicator which pulses
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* in the middle of the high and low periods of the clock.
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* in the middle of the high and low periods of the clock.
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*/
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*/
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module I2C_Clock(
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module I2C_Clock(
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input clock, // 100 MHz
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input clock, // 100 MHz
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input reset,
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input reset,
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inout scl, // A 100 kHz clock
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inout scl, // A 100 kHz clock
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output scl_tick_90 // A pulse indicating the middle of the +/- scl levels
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output scl_tick_90 // A pulse indicating the middle of the +/- scl levels
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);
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);
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reg [7:0] count_4x;
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reg [7:0] count_4x;
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always @(posedge clock) begin
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always @(posedge clock) begin
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//count_4x <= (reset) ? 8'h00 : (scl) ? count_4x + 1 : count_4x;
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//count_4x <= (reset) ? 8'h00 : (scl) ? count_4x + 1 : count_4x;
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count_4x <= (reset) ? 8'h00 : count_4x + 1; // XXX SIMULATION ONLY
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count_4x <= (reset) ? 8'h00 : count_4x + 1; // XXX SIMULATION ONLY
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end
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end
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// A single pulse once every 250 cycles
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// A single pulse once every 250 cycles
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wire tick_4x = (count_4x == 8'hFA);
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wire tick_4x = (count_4x == 8'hFA);
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reg [1:0] state;
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reg [1:0] state;
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always @(posedge clock) begin
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always @(posedge clock) begin
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if (reset) begin
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if (reset) begin
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state <= 2'b00;
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state <= 2'b00;
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end
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end
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else begin
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else begin
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case (state)
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case (state)
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2'd0 : state <= (tick_4x) ? 2'd1 : 2'd0;
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2'd0 : state <= (tick_4x) ? 2'd1 : 2'd0;
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2'd1 : state <= (tick_4x) ? 2'd2 : 2'd1;
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2'd1 : state <= (tick_4x) ? 2'd2 : 2'd1;
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2'd2 : state <= (tick_4x) ? 2'd3 : 2'd2;
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2'd2 : state <= (tick_4x) ? 2'd3 : 2'd2;
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2'd3 : state <= (tick_4x) ? 2'd0 : 2'd3;
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2'd3 : state <= (tick_4x) ? 2'd0 : 2'd3;
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endcase
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endcase
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end
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end
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end
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end
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assign scl = ((state == 2'd0) || (state == 2'd1));
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assign scl = ((state == 2'd0) || (state == 2'd1));
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assign scl_tick_90 = tick_4x & ((state == 2'd0) || (state == 2'd2));
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assign scl_tick_90 = tick_4x & ((state == 2'd0) || (state == 2'd2));
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endmodule
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endmodule
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No newline at end of file
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