`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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/*
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/*
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* File : ALU.v
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* File : ALU.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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*
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* Modification History:
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* Modification History:
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* Rev Date Initials Description of Change
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* Rev Date Initials Description of Change
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* 1.0 7-Jun-2011 GEA Initial design.
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* 1.0 7-Jun-2011 GEA Initial design.
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* 2.0 26-Jul-2012 GEA Many changes have been made.
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* 2.0 26-Jul-2012 GEA Many changes have been made.
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*
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*
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* Standards/Formatting:
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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* Verilog 2001, 4 soft tab, wide column.
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*
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*
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* Description:
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* Description:
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* An Arithmetic Logic Unit for a MIPS32 processor. This module computes all
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* An Arithmetic Logic Unit for a MIPS32 processor. This module computes all
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* arithmetic operations, including the following:
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* arithmetic operations, including the following:
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*
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*
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* Add, Subtract, Multiply, And, Or, Nor, Xor, Shift, Count leading 1s/0s.
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* Add, Subtract, Multiply, And, Or, Nor, Xor, Shift, Count leading 1s/0s.
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*/
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*/
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module ALU(
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module ALU(
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input clock,
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input clock,
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input reset,
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input reset,
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input EX_Stall,
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input EX_Stall,
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input EX_Flush,
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input EX_Flush,
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input [31:0] A, B,
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input [31:0] A, B,
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input [4:0] Operation,
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input [4:0] Operation,
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input signed [4:0] Shamt,
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input signed [4:0] Shamt,
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output reg signed [31:0] Result,
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output reg signed [31:0] Result,
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output BZero, // Used for Movc
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output BZero, // Used for Movc
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output reg EXC_Ov
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output reg EXC_Ov
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);
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);
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`include "MIPS_Parameters.v"
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`include "MIPS_Parameters.v"
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/***
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/***
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Performance Notes:
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Performance Notes:
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The ALU is the longest delay path in the Execute stage, and one of the longest
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The ALU is the longest delay path in the Execute stage, and one of the longest
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in the entire processor. This path varies based on the logic blocks that are
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in the entire processor. This path varies based on the logic blocks that are
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chosen to implement various functions, but there is certainly room to improve
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chosen to implement various functions, but there is certainly room to improve
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the speed of arithmetic operations. The ALU could also be placed in a separate
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the speed of arithmetic operations. The ALU could also be placed in a separate
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pipeline stage after the Execute forwarding has completed.
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pipeline stage after the Execute forwarding has completed.
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***/
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***/
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wire signed [31:0] As = A;
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wire signed [31:0] As = A;
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wire signed [31:0] Bs = B;
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wire signed [31:0] Bs = B;
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|
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reg [63:0] HILO;
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reg [63:0] HILO;
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wire [31:0] HI = HILO[63:32];
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wire [31:0] HI = HILO[63:32];
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wire [31:0] LO = HILO[31:0];
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wire [31:0] LO = HILO[31:0];
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wire HILO_Commit = ~(EX_Stall | EX_Flush);
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wire HILO_Commit = ~(EX_Stall | EX_Flush);
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|
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wire AddSub_Add = ((Operation == AluOp_Add) | (Operation == AluOp_Addu));
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wire AddSub_Add = ((Operation == AluOp_Add) | (Operation == AluOp_Addu));
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wire signed [31:0] AddSub_Result = (AddSub_Add) ? (A + B) : (A - B);
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wire signed [31:0] AddSub_Result = (AddSub_Add) ? (A + B) : (A - B);
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|
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wire signed [63:0] Mult_Result = As * Bs;
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wire signed [63:0] Mult_Result = As * Bs;
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wire [63:0] Multu_Result = A * B;
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wire [63:0] Multu_Result = A * B;
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reg [5:0] CLO_Result, CLZ_Result;
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reg [5:0] CLO_Result, CLZ_Result;
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assign BZero = (B == 32'h00000000);
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assign BZero = (B == 32'h00000000);
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always @(*) begin
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always @(*) begin
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case (Operation)
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case (Operation)
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AluOp_Add : Result <= AddSub_Result;
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AluOp_Add : Result <= AddSub_Result;
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AluOp_Addu : Result <= AddSub_Result;
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AluOp_Addu : Result <= AddSub_Result;
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AluOp_And : Result <= A & B;
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AluOp_And : Result <= A & B;
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AluOp_Clo : Result <= {26'b0, CLO_Result};
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AluOp_Clo : Result <= {26'b0, CLO_Result};
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AluOp_Clz : Result <= {26'b0, CLZ_Result};
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AluOp_Clz : Result <= {26'b0, CLZ_Result};
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AluOp_Div : Result <= 32'hdeafbeef; // XXX implement division
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AluOp_Div : Result <= 32'hdeafbeef; // XXX implement division
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AluOp_Divu : Result <= 32'hdeadbeef; // XXX implement division
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AluOp_Divu : Result <= 32'hdeadbeef; // XXX implement division
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AluOp_Mfhi : Result <= HI;
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AluOp_Mfhi : Result <= HI;
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AluOp_Mflo : Result <= LO;
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AluOp_Mflo : Result <= LO;
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AluOp_Mul : Result <= Mult_Result[31:0];
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AluOp_Mul : Result <= Mult_Result[31:0];
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AluOp_Nor : Result <= ~(A | B);
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AluOp_Nor : Result <= ~(A | B);
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AluOp_Or : Result <= A | B;
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AluOp_Or : Result <= A | B;
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AluOp_Sll : Result <= B << Shamt;
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AluOp_Sll : Result <= B << Shamt;
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AluOp_Sllc : Result <= {B[15:0], 16'b0};
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AluOp_Sllc : Result <= {B[15:0], 16'b0};
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AluOp_Sllv : Result <= B << A[4:0];
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AluOp_Sllv : Result <= B << A[4:0];
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AluOp_Slt : Result <= (As < Bs) ? 32'h00000001 : 32'h00000000;
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AluOp_Slt : Result <= (As < Bs) ? 32'h00000001 : 32'h00000000;
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AluOp_Sltu : Result <= (A < B) ? 32'h00000001 : 32'h00000000;
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AluOp_Sltu : Result <= (A < B) ? 32'h00000001 : 32'h00000000;
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AluOp_Sra : Result <= Bs >>> Shamt;
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AluOp_Sra : Result <= Bs >>> Shamt;
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AluOp_Srav : Result <= Bs >>> As[4:0];
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AluOp_Srav : Result <= Bs >>> As[4:0];
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AluOp_Srl : Result <= B >> Shamt;
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AluOp_Srl : Result <= B >> Shamt;
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AluOp_Srlv : Result <= B >> A[4:0];
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AluOp_Srlv : Result <= B >> A[4:0];
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AluOp_Sub : Result <= AddSub_Result;
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AluOp_Sub : Result <= AddSub_Result;
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AluOp_Subu : Result <= AddSub_Result;
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AluOp_Subu : Result <= AddSub_Result;
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AluOp_Xor : Result <= A ^ B;
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AluOp_Xor : Result <= A ^ B;
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default : Result <= 32'bx;
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default : Result <= 32'bx;
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endcase
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endcase
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end
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end
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always @(posedge clock) begin
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always @(posedge clock) begin
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if (reset) begin
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if (reset) begin
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HILO <= 64'h00000000_00000000;
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HILO <= 64'h00000000_00000000;
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end
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end
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else if (HILO_Commit) begin
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else if (HILO_Commit) begin
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case (Operation)
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case (Operation)
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AluOp_Mult : HILO <= Mult_Result;
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AluOp_Mult : HILO <= Mult_Result;
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AluOp_Multu : HILO <= Multu_Result;
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AluOp_Multu : HILO <= Multu_Result;
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AluOp_Madd : HILO <= HILO + Mult_Result;
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AluOp_Madd : HILO <= HILO + Mult_Result;
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AluOp_Maddu : HILO <= HILO + Multu_Result;
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AluOp_Maddu : HILO <= HILO + Multu_Result;
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AluOp_Msub : HILO <= HILO - Mult_Result;
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AluOp_Msub : HILO <= HILO - Mult_Result;
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AluOp_Msubu : HILO <= HILO - Multu_Result;
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AluOp_Msubu : HILO <= HILO - Multu_Result;
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AluOp_Mthi : HILO <= {A, LO};
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AluOp_Mthi : HILO <= {A, LO};
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AluOp_Mtlo : HILO <= {HI, B};
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AluOp_Mtlo : HILO <= {HI, B};
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default : HILO <= HILO;
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default : HILO <= HILO;
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endcase
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endcase
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end
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end
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else begin
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else begin
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HILO <= HILO;
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HILO <= HILO;
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end
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end
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end
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end
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// Detect overflow for signed operations. Note that MIPS32 has no overflow
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// Detect overflow for signed operations. Note that MIPS32 has no overflow
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// detection for multiplication/division operations.
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// detection for multiplication/division operations.
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always @(*) begin
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always @(*) begin
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case (Operation)
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case (Operation)
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AluOp_Add : EXC_Ov <= ((A[31] ~^ B[31]) & (A[31] ^ AddSub_Result[31]));
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AluOp_Add : EXC_Ov <= ((A[31] ~^ B[31]) & (A[31] ^ AddSub_Result[31]));
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AluOp_Sub : EXC_Ov <= ((A[31] ^ B[31]) & (A[31] ^ AddSub_Result[31]));
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AluOp_Sub : EXC_Ov <= ((A[31] ^ B[31]) & (A[31] ^ AddSub_Result[31]));
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default : EXC_Ov <= 0;
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default : EXC_Ov <= 0;
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endcase
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endcase
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end
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end
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// Count Leading Ones
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// Count Leading Ones
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always @(A) begin
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always @(A) begin
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casex (A)
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casex (A)
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32'b0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd0;
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32'b0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd0;
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32'b10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd1;
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32'b10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd1;
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32'b110x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd2;
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32'b110x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd2;
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32'b1110_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd3;
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32'b1110_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd3;
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32'b1111_0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd4;
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32'b1111_0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd4;
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32'b1111_10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd5;
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32'b1111_10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd5;
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32'b1111_110x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd6;
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32'b1111_110x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd6;
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32'b1111_1110_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd7;
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32'b1111_1110_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd7;
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32'b1111_1111_0xxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd8;
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32'b1111_1111_0xxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd8;
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32'b1111_1111_10xx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd9;
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32'b1111_1111_10xx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd9;
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32'b1111_1111_110x_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd10;
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32'b1111_1111_110x_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd10;
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32'b1111_1111_1110_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd11;
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32'b1111_1111_1110_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd11;
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32'b1111_1111_1111_0xxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd12;
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32'b1111_1111_1111_0xxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd12;
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32'b1111_1111_1111_10xx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd13;
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32'b1111_1111_1111_10xx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd13;
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32'b1111_1111_1111_110x_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd14;
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32'b1111_1111_1111_110x_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd14;
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32'b1111_1111_1111_1110_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd15;
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32'b1111_1111_1111_1110_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd15;
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32'b1111_1111_1111_1111_0xxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd16;
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32'b1111_1111_1111_1111_0xxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd16;
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32'b1111_1111_1111_1111_10xx_xxxx_xxxx_xxxx : CLO_Result <= 6'd17;
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32'b1111_1111_1111_1111_10xx_xxxx_xxxx_xxxx : CLO_Result <= 6'd17;
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32'b1111_1111_1111_1111_110x_xxxx_xxxx_xxxx : CLO_Result <= 6'd18;
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32'b1111_1111_1111_1111_110x_xxxx_xxxx_xxxx : CLO_Result <= 6'd18;
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32'b1111_1111_1111_1111_1110_xxxx_xxxx_xxxx : CLO_Result <= 6'd19;
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32'b1111_1111_1111_1111_1110_xxxx_xxxx_xxxx : CLO_Result <= 6'd19;
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32'b1111_1111_1111_1111_1111_0xxx_xxxx_xxxx : CLO_Result <= 6'd20;
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32'b1111_1111_1111_1111_1111_0xxx_xxxx_xxxx : CLO_Result <= 6'd20;
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32'b1111_1111_1111_1111_1111_10xx_xxxx_xxxx : CLO_Result <= 6'd21;
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32'b1111_1111_1111_1111_1111_10xx_xxxx_xxxx : CLO_Result <= 6'd21;
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32'b1111_1111_1111_1111_1111_110x_xxxx_xxxx : CLO_Result <= 6'd22;
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32'b1111_1111_1111_1111_1111_110x_xxxx_xxxx : CLO_Result <= 6'd22;
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32'b1111_1111_1111_1111_1111_1110_xxxx_xxxx : CLO_Result <= 6'd23;
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32'b1111_1111_1111_1111_1111_1110_xxxx_xxxx : CLO_Result <= 6'd23;
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32'b1111_1111_1111_1111_1111_1111_0xxx_xxxx : CLO_Result <= 6'd24;
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32'b1111_1111_1111_1111_1111_1111_0xxx_xxxx : CLO_Result <= 6'd24;
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32'b1111_1111_1111_1111_1111_1111_10xx_xxxx : CLO_Result <= 6'd25;
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32'b1111_1111_1111_1111_1111_1111_10xx_xxxx : CLO_Result <= 6'd25;
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32'b1111_1111_1111_1111_1111_1111_110x_xxxx : CLO_Result <= 6'd26;
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32'b1111_1111_1111_1111_1111_1111_110x_xxxx : CLO_Result <= 6'd26;
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32'b1111_1111_1111_1111_1111_1111_1110_xxxx : CLO_Result <= 6'd27;
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32'b1111_1111_1111_1111_1111_1111_1110_xxxx : CLO_Result <= 6'd27;
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32'b1111_1111_1111_1111_1111_1111_1111_0xxx : CLO_Result <= 6'd28;
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32'b1111_1111_1111_1111_1111_1111_1111_0xxx : CLO_Result <= 6'd28;
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32'b1111_1111_1111_1111_1111_1111_1111_10xx : CLO_Result <= 6'd29;
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32'b1111_1111_1111_1111_1111_1111_1111_10xx : CLO_Result <= 6'd29;
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32'b1111_1111_1111_1111_1111_1111_1111_110x : CLO_Result <= 6'd30;
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32'b1111_1111_1111_1111_1111_1111_1111_110x : CLO_Result <= 6'd30;
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32'b1111_1111_1111_1111_1111_1111_1111_1110 : CLO_Result <= 6'd31;
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32'b1111_1111_1111_1111_1111_1111_1111_1110 : CLO_Result <= 6'd31;
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32'b1111_1111_1111_1111_1111_1111_1111_1111 : CLO_Result <= 6'd32;
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32'b1111_1111_1111_1111_1111_1111_1111_1111 : CLO_Result <= 6'd32;
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default : CLO_Result <= 6'd0;
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default : CLO_Result <= 6'd0;
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endcase
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endcase
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end
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end
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// Count Leading Zeros
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// Count Leading Zeros
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always @(A) begin
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always @(A) begin
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casex (A)
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casex (A)
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32'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd0;
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32'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd0;
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32'b01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd1;
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32'b01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd1;
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32'b001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd2;
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32'b001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd2;
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32'b0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd3;
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32'b0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd3;
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32'b0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd4;
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32'b0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd4;
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32'b0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd5;
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32'b0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd5;
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32'b0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd6;
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32'b0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd6;
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32'b0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd7;
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32'b0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd7;
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32'b0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd8;
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32'b0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd8;
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32'b0000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd9;
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32'b0000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd9;
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32'b0000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd10;
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32'b0000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd10;
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32'b0000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd11;
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32'b0000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd11;
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32'b0000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd12;
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32'b0000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd12;
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32'b0000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd13;
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32'b0000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd13;
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32'b0000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd14;
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32'b0000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd14;
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32'b0000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd15;
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32'b0000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd15;
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32'b0000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd16;
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32'b0000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd16;
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32'b0000_0000_0000_0000_01xx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd17;
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32'b0000_0000_0000_0000_01xx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd17;
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32'b0000_0000_0000_0000_001x_xxxx_xxxx_xxxx : CLZ_Result <= 6'd18;
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32'b0000_0000_0000_0000_001x_xxxx_xxxx_xxxx : CLZ_Result <= 6'd18;
|
32'b0000_0000_0000_0000_0001_xxxx_xxxx_xxxx : CLZ_Result <= 6'd19;
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32'b0000_0000_0000_0000_0001_xxxx_xxxx_xxxx : CLZ_Result <= 6'd19;
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32'b0000_0000_0000_0000_0000_1xxx_xxxx_xxxx : CLZ_Result <= 6'd20;
|
32'b0000_0000_0000_0000_0000_1xxx_xxxx_xxxx : CLZ_Result <= 6'd20;
|
32'b0000_0000_0000_0000_0000_01xx_xxxx_xxxx : CLZ_Result <= 6'd21;
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32'b0000_0000_0000_0000_0000_01xx_xxxx_xxxx : CLZ_Result <= 6'd21;
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32'b0000_0000_0000_0000_0000_001x_xxxx_xxxx : CLZ_Result <= 6'd22;
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32'b0000_0000_0000_0000_0000_001x_xxxx_xxxx : CLZ_Result <= 6'd22;
|
32'b0000_0000_0000_0000_0000_0001_xxxx_xxxx : CLZ_Result <= 6'd23;
|
32'b0000_0000_0000_0000_0000_0001_xxxx_xxxx : CLZ_Result <= 6'd23;
|
32'b0000_0000_0000_0000_0000_0000_1xxx_xxxx : CLZ_Result <= 6'd24;
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32'b0000_0000_0000_0000_0000_0000_1xxx_xxxx : CLZ_Result <= 6'd24;
|
32'b0000_0000_0000_0000_0000_0000_01xx_xxxx : CLZ_Result <= 6'd25;
|
32'b0000_0000_0000_0000_0000_0000_01xx_xxxx : CLZ_Result <= 6'd25;
|
32'b0000_0000_0000_0000_0000_0000_001x_xxxx : CLZ_Result <= 6'd26;
|
32'b0000_0000_0000_0000_0000_0000_001x_xxxx : CLZ_Result <= 6'd26;
|
32'b0000_0000_0000_0000_0000_0000_0001_xxxx : CLZ_Result <= 6'd27;
|
32'b0000_0000_0000_0000_0000_0000_0001_xxxx : CLZ_Result <= 6'd27;
|
32'b0000_0000_0000_0000_0000_0000_0000_1xxx : CLZ_Result <= 6'd28;
|
32'b0000_0000_0000_0000_0000_0000_0000_1xxx : CLZ_Result <= 6'd28;
|
32'b0000_0000_0000_0000_0000_0000_0000_01xx : CLZ_Result <= 6'd29;
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32'b0000_0000_0000_0000_0000_0000_0000_01xx : CLZ_Result <= 6'd29;
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32'b0000_0000_0000_0000_0000_0000_0000_001x : CLZ_Result <= 6'd30;
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32'b0000_0000_0000_0000_0000_0000_0000_001x : CLZ_Result <= 6'd30;
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32'b0000_0000_0000_0000_0000_0000_0000_0001 : CLZ_Result <= 6'd31;
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32'b0000_0000_0000_0000_0000_0000_0000_0001 : CLZ_Result <= 6'd31;
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32'b0000_0000_0000_0000_0000_0000_0000_0000 : CLZ_Result <= 6'd32;
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32'b0000_0000_0000_0000_0000_0000_0000_0000 : CLZ_Result <= 6'd32;
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default : CLZ_Result <= 6'd0;
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default : CLZ_Result <= 6'd0;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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