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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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/*
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/*
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* File : Register.v
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* File : Register.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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*
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* Modification History:
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* Modification History:
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* Rev Date Initials Description of Change
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* Rev Date Initials Description of Change
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* 1.0 7-Jun-2011 GEA Initial design.
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* 1.0 7-Jun-2011 GEA Initial design.
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*
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*
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* Standards/Formatting:
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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* Verilog 2001, 4 soft tab, wide column.
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*
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*
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* Description:
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* Description:
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* A variable-width register (d flip-flop) with configurable initial
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* A variable-width register (d flip-flop) with configurable initial
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* value. Default is 32-bit width and 0s for initial value.
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* value. Default is 32-bit width and 0s for initial value.
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*/
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*/
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module Register #(parameter WIDTH = 32, INIT = 0)(
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module Register #(parameter WIDTH = 32, INIT = 0)(
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input clock,
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input clock,
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input reset,
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input reset,
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input enable,
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input enable,
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input [(WIDTH-1):0] D,
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input [(WIDTH-1):0] D,
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output reg [(WIDTH-1):0] Q
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output reg [(WIDTH-1):0] Q
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);
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);
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initial
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initial
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Q = INIT;
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Q = INIT;
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always @(posedge clock) begin
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always @(posedge clock) begin
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Q <= (reset) ? INIT : ((enable) ? D : Q);
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Q <= (reset) ? INIT : ((enable) ? D : Q);
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end
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end
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endmodule
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endmodule
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