`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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/*
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/*
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* File : Piezo.v
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* File : Piezo.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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*
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* Modification History:
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* Modification History:
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* Rev Date Initials Description of Change
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* Rev Date Initials Description of Change
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* 1.0 11-Jun-2012 GEA Initial design.
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* 1.0 11-Jun-2012 GEA Initial design.
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*
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*
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* Standards/Formatting:
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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* Verilog 2001, 4 soft tab, wide column.
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*
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*
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* Description:
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* Description:
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* A sound driver for a piezo-electric transducer (or other
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* A sound driver for a piezo-electric transducer (or other
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* oscillating device). When enabled, the output oscillates
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* oscillating device). When enabled, the output oscillates
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* between high and low, switching at a rate determined by the
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* between high and low, switching at a rate determined by the
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* 'count' register and clock frequency. The output is enabled
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* 'count' register and clock frequency. The output is enabled
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* when the highest bit is set on a Write.
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* when the highest bit is set on a Write.
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*/
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*/
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module Piezo_Driver(
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module Piezo_Driver(
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input clock,
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input clock,
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input reset,
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input reset,
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input [24:0] data,
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input [24:0] data,
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input Write,
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input Write,
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output reg Ack,
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output reg Ack,
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output reg Piezo
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output reg Piezo
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);
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);
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reg [23:0] count;
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reg [23:0] count;
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reg [23:0] compare;
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reg [23:0] compare;
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reg enabled;
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reg enabled;
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always @(posedge clock) begin
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always @(posedge clock) begin
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count <= (reset | (count == compare)) ? 24'h000000 : count + 1;
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count <= (reset | (count == compare)) ? 24'h000000 : count + 1;
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compare <= (reset) ? 24'h000000 : ((Write) ? data[23:0] : compare);
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compare <= (reset) ? 24'h000000 : ((Write) ? data[23:0] : compare);
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enabled <= (reset) ? 0 : ((Write) ? data[24] : enabled);
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enabled <= (reset) ? 0 : ((Write) ? data[24] : enabled);
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Piezo <= (reset | ~enabled) ? 0 : ((count == compare) ? ~Piezo : Piezo);
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Piezo <= (reset | ~enabled) ? 0 : ((count == compare) ? ~Piezo : Piezo);
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Ack <= (reset) ? 0 : Write;
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Ack <= (reset) ? 0 : Write;
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end
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end
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endmodule
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endmodule
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