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[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC/] [MIPS32-Pipelined-Hw/] [src/] [Simulation/] [Top_Tester.v] - Diff between revs 2 and 3

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Rev 2 Rev 3
`timescale 1ns / 1ps
`timescale 1ns / 1ps
 
 
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Company: 
// Engineer:
// Engineer:
//
//
// Create Date:   12:38:44 09/10/2012
// Create Date:   12:38:44 09/10/2012
// Design Name:   Top
// Design Name:   Top
// Module Name:   C:/root/Work/Gauss/Final/Hardware/XUM_Singlecore/MIPS32-Pipelined-Hw/src/Simulation/Top_Tester.v
// Module Name:   C:/root/Work/Gauss/Final/Hardware/XUM_Singlecore/MIPS32-Pipelined-Hw/src/Simulation/Top_Tester.v
// Project Name:  MIPS32-Pipelined-Hw
// Project Name:  MIPS32-Pipelined-Hw
// Target Device:  
// Target Device:  
// Tool versions:  
// Tool versions:  
// Description: 
// Description: 
//
//
// Verilog Test Fixture created by ISE for module: Top
// Verilog Test Fixture created by ISE for module: Top
//
//
// Dependencies:
// Dependencies:
// 
// 
// Revision:
// Revision:
// Revision 0.01 - File Created
// Revision 0.01 - File Created
// Additional Comments:
// Additional Comments:
// 
// 
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
 
 
module Top_Tester;
module Top_Tester;
 
 
        // Inputs
    // Inputs
        reg clock_100MHz;
    reg clock_100MHz;
        reg reset_n;
    reg reset_n;
        reg [7:0] Switch;
    reg [7:0] Switch;
        reg UART_Rx;
    reg UART_Rx;
 
 
        // Outputs
    // Outputs
        wire [14:0] LED;
    wire [14:0] LED;
        wire [6:0] LCD;
    wire [6:0] LCD;
        wire UART_Tx;
    wire UART_Tx;
        wire Piezo;
    wire Piezo;
 
 
        // Bidirs
    // Bidirs
        wire i2c_scl;
    wire i2c_scl;
        wire i2c_sda;
    wire i2c_sda;
 
 
        // Instantiate the Unit Under Test (UUT)
    // Instantiate the Unit Under Test (UUT)
        Top uut (
    Top uut (
                .clock_100MHz(clock_100MHz),
        .clock_100MHz(clock_100MHz),
                .reset_n(reset_n),
        .reset_n(reset_n),
                .Switch(Switch),
        .Switch(Switch),
                .LED(LED),
        .LED(LED),
                .LCD(LCD),
        .LCD(LCD),
                .UART_Rx(UART_Rx),
        .UART_Rx(UART_Rx),
                .UART_Tx(UART_Tx),
        .UART_Tx(UART_Tx),
                .i2c_scl(i2c_scl),
        .i2c_scl(i2c_scl),
                .i2c_sda(i2c_sda),
        .i2c_sda(i2c_sda),
                .Piezo(Piezo)
        .Piezo(Piezo)
        );
    );
    integer i;
    integer i;
 
 
        initial begin
    initial begin
                // Initialize Inputs
        // Initialize Inputs
                clock_100MHz = 0;
        clock_100MHz = 0;
                reset_n = 0;
        reset_n = 0;
                Switch = 0;
        Switch = 0;
                UART_Rx = 0;
        UART_Rx = 0;
 
 
                // Wait 100 ns for global reset to finish
        // Wait 100 ns for global reset to finish
                #100;
        #100;
 
 
                // Add stimulus here
        // Add stimulus here
        for (i=0; i<900000; i=i+1) begin
        for (i=0; i<900000; i=i+1) begin
            reset_n = (i < 28) ? 0 : 1;
            reset_n = (i < 28) ? 0 : 1;
            clock_100MHz = ~clock_100MHz;
            clock_100MHz = ~clock_100MHz;
            if (i > 4000) Switch <= 8'h00;
            if (i > 4000) Switch <= 8'h00;
            if (i > 100000) i = i - 1;
            if (i > 100000) i = i - 1;
            #5;
            #5;
        end
        end
        end
    end
 
 
endmodule
endmodule
 
 
 
 

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